LTC1439IGW#PBF Datasheet LTC1438IG-ADJ#PBF, LTC1439IG#PBF, LTC1439CGW#PBF | P10-P12

LTC1438/LTC1439

14389fb

OPERATION

Main Control Loop

The LTC1438/LTC1439 use a constant frequency, current

mode step-down architecture. During normal operation,

the top MOSFET is turned on each cycle when the oscillator

sets the RS latch and turned off when the main current

comparator I1 resets the RS latch. The peak inductor

current at which I1 resets the RS latch is controlled by the

voltage on the I

TH1

TH2

) pin, which is the output of each

error amplifier (EA). The V

PROG1

pin, described in the Pin

Functions, allows the EA to receive a selectively attenuated

output feedback voltage V

FB1

from the SENSE

–

1 pin while

PROG2

and V

OSENSE2

allow EA to receive an output feed-

back voltage V

FB2

from either internal or external resistive

dividers on the second controller. When the load current

increases, it causes a slight decrease in V

relative to the

1.19V reference, which in turn causes the I

TH1

TH2

)

voltage to increase until the average inductor current

matches the new load current. After the large top MOSFET

has turned off, the bottom MOSFET is turned on until either

the inductor current starts to reverse, as indicated by

current comparator I2, or the beginning of the next cycle.

The top MOSFET drivers are biased from floating boot

strap capacitor C

, which normally is recharged during

each Off cycle. When V

decreases to a voltage close to

OUT

, however, the loop may enter dropout and attempt to

turn on the top MOSFET continuously. The dropout detec-

tor counts the number of oscillator cycles that the top

MOSFET remains on and periodically forces a brief off

period to allow C

to recharge.

The main control loop is shut down by pulling the RUN/

SS1 (RUN/SS2) pin low. Releasing RUN/SS1 (RUN/SS2)

allows an internal 3µA current source to charge soft start

capacitor C

. When C

reaches 1.3V, the main control

loop is enabled with the I

TH1

TH2

) voltage clamped at

approximately 30% of its maximum value. As C

contin-

ues to charge, I

TH1

TH2

) is gradually released allowing

normal operation to resume. When both RUN/SS1 and

RUN/SS2 are low, all LTC1438/LTC1439 functions are

shut down. Refer to the LTC1538-AUX/LTC1539 data

sheet for 5V keep-alive applications.

Comparator OV guards against transient overshoots > 7.5%

by turning off the top MOSFET and keeping it off until the

fault is removed.

Low Current Operation

Adaptive Power mode allows the LTC1439 to automati-

cally change between two output stages sized for different

load currents. The TGL1 (TGL2) and BG1 (BG2) pins drive

large synchronous N-channel MOSFETs for operation at

high currents, while the TGS1 (TGS2) pin drives a much

smaller N-channel MOSFET used in conjunction with a

Schottky diode for operation at low currents. This allows

the loop to continue to operate at normal operating fre-

quency as the load current decreases without incurring the

large MOSFET gate charge losses. If the TGS1 (TGS2) pin

is left open, the loop defaults to Burst Mode operation in

which the large MOSFETs operate intermittently based on

load demand.

Adaptive Power mode provides constant frequency opera-

tion down to approximately 1% of rated load current. This

results in an order of magnitude reduction of load current

before Burst Mode operation commences. Without the

small MOSFET (i.e., no Adaptive Power mode) the transi-

tion to Burst Mode operation is approximately 10% of

rated load current.

The transition to low current operation begins when com-

parator I2 detects current reversal and turns off the

bottom MOSFET. If the voltage across R

SENSE

does not

exceed the hysteresis of I2 (approximately 20mV) for one

full cycle, then on following cycles the top drive is routed

to the small MOSFET at the TGS1 (TGS2) pin and the BG1

(BG2) pin is disabled. This continues until an inductor

current peak exceeds 20mV/R

SENSE

or the I

TH1

TH2

)

voltage exceeds 0.6V, either of which causes drive to be

returned to the TGL1 (TGL2) pin on the next cycle.

Two conditions can force continuous synchronous opera-

tion, even when the load current would otherwise dictate

low current operation. One is when the common mode

voltage of the SENSE

1 (SENSE

2) and SENSE

–

(SENSE

–

2) pins are below 1.4V, and the other is when the

SFB1 pin is below 1.19V. The latter condition is used to

assist in secondary winding regulation, as described in the

Applications Information section.

(Refer to Functional Diagram)

LTC1438/LTC1439

14389fb

OPERATION

the AUXDR pin is above 9.5V to allow regulated 12V

VPP supplies to be easily implemented. When AUXDR is

below 8.5V an external feedback divider may be used to set

other output voltages. Taking the AUXON pin low shuts

down the auxiliary regulator providing a convenient logic-

controlled power supply.

The AUX block can be used as a comparator having its

inverting input tied to the internal 1.19V reference. The

AUXDR pin is used as the output and requires an external

pull-up to a supply of less than 8.5V in order to inhibit the

invoking of the internal resistive divider.

INTV

/ EXTV

Power

Power for the top and bottom MOSFET drivers and most

of the other LTC1438/LTC1439 circuitry is derived from

the INTV

pin. The bottom MOSFET driver supply is also

connected to INTV

. When the EXTV

pin is left open, an

internal 5V low dropout regulator supplies INTV

power.

If EXTV

is taken above 4.8V, the 5V regulator is turned

off and an internal switch is turned on to connect EXTV

to INTV

. This allows the INTV

power to be derived

from a high efficiency external source such as the output

of the regulator itself or a secondary winding, as described

in the Applications Information section.

(Refer to Functional Diagram)

Frequency Synchronization

A Phase-Locked Loop (PLL) is available on the LTC1439

to allow the oscillator to be synchronized to an external

source connected to the PLLIN pin. The output of the

phase detector at the PLL LPF pin is also the control input

of the oscillator, which operates over a 0V to 2.4V range

corresponding to –30% to 30% in frequency. When

locked, the PLL aligns the turn-on of the top MOSFET to

the rising edge of the synchronizing signal. When PLLIN

is left open, PLL LPF goes low, forcing the oscillator to

minimum frequency.

Power-On Reset

The POR2 pin is an open drain output which pulls low

when the main regulator output voltage of the second

controller is out of regulation. When the output voltage

rises to within 7.5% of regulation, a timer is started which

releases POR2 after 2

(65536) oscillator cycles. This

function is not available on the LTC1438X.

Auxiliary Linear Regulator

The auxiliary linear regulator in the LTC1439 controls an

external PNP transistor for operation up to 500mA. A

precise internal AUXFB resistive divider is invoked when

LTC1438/LTC1439

14389fb

APPLICATIONS INFORMATION

WUU

A graph for selecting C

OSC

vs frequency is given in Figure

2. As the operating frequency is increased the gate charge

losses will be higher, reducing efficiency (see Efficiency

Considerations). The maximum recommended switching

frequency is 400kHz. When using Figure 2 for

synchronizable applications, choose C

OSC

corresponding

to a frequency approximately 30% below your center

frequency. (See Phase-Locked Loop and Frequency

Sychronization).

OPERATING FREQUENCY (kHz)

OSC

VALUE (pF)

300

250

200

150

100

100 200 300 400

LTC1435 • F02

5000

PLLLPF

= 0V

Figure 2. Timing Capacitor Value

Inductor Value Calculation

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

MOSFET gate charge losses. In addition to this basic trade

off, the effect of inductor value on ripple current and low

current operation must also be considered.

The inductor value has a direct effect on ripple current. The

inductor ripple current ∆I

decreases with higher induc-

tance or frequency and increases with higher V

or V

OUT

∆I

L OUT

OUT

⎛

⎝

⎜

⎞

⎠

⎟

()()

–

The basic LTC1439 application circuit is shown in Fig-

ure 1. External component selection is driven by the load

requirement and begins with the selection of R

SENSE

. Once

SENSE

is known, C

OSC

and L can be chosen. Next, the

power MOSFETs and D1 are selected. Finally, C

and C

OUT

are selected. The circuit shown in Figure 1 can be config-

ured for operation up to an input voltage of 28V (limited by

the external MOSFETs).

SENSE

Selection for Output Current

SENSE

is chosen based on the required output current.

The LTC1438/LTC1439 current comparator has a maxi-

mum threshold of 150mV/R

SENSE

and an input common

mode range of SGND to INTV

. The current comparator

threshold sets the peak of the inductor current, yielding a

maximum average output current I

MAX

equal to the peak

value less half the peak-to-peak ripple current, ∆I

Allowing some margin for variations in the LTC1438/

LTC1439 and external component values yield:

SENSE

MAX

100

The LTC1438/LTC1439 work well with values of R

SENSE

from 0.005Ω to 0.2Ω.

OSC

Selection for Operating Frequency

The LTC1438/LTC1439 use a constant frequency architec-

ture with the frequency determined by an external oscilla-

tor capacitor on C

OSC

. Each time the topside MOSFET

turns on, the voltage on C

OSC

is reset to ground. During the

on-time, C

OSC

is charged by a fixed current plus an

additional current which is proportional to the output

voltage of the phase detector (V

PLLLPF

)(LTC1439 only).

When the voltage on the capacitor reaches 1.19V, C

OSC

reset to ground. The process then repeats.

The value of C

OSC

is calculated from the desired operating

frequency. Assuming the phase-locked loop has no exter-

nal oscillator input (V

PLLLPF

= 0V):

CpF

OSC

()

.( )

⎡

⎣

⎢

⎤

⎦

⎥

−

13710

Frequency (kHz)

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Switching Voltage Regulators 2x Hi Eff, L N, Sync Buck Sw Regs

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