LTC2453
12
2453fc
ADC input pins. This capacitor is placed in parallel with
the ADC input parasitic capacitance C
PAR
. Depending
on the PCB layout, C
PAR
has typical values between 2pF
and 15pF. In addition, the equivalent circuit of Figure 9
includes the converter equivalent internal resistor R
SW
and sampling capacitor C
EQ
.
There are some immediate trade-offs in R
S
and C
IN
without
needing a full circuit analysis. Increasing R
S
and C
IN
can
give the following benefits:
1) Due to the LTC2453’s input sampling algorithm, the
input current drawn by either V
IN
+
or V
IN
–
over a con-
version cycle is 50nA. A high R
S
• C
IN
attenuates the
high frequency components of the input current, and
R
S
values up to 1k result in <1LSB error.
2) The bandwidth from V
SIG
is reduced at the input pins
(IN
+
, IN
–
). This bandwidth reduction isolates the ADC
from high frequency signals, and as such provides
simple antialiasing and input noise reduction.
3) Switching transients generated by the ADC are attenu-
ated before they go back to the signal source.
4) A large C
IN
gives a better AC ground at the input pins,
helping reduce reflections back to the signal source.
5) Increasing R
S
protects the ADC by limiting the current
during an outside-the-rails fault condition.
There is a limit to how large R
S
• C
IN
should be for a given
application. Increasing R
S
beyond a given point increases
Figure 10. Measured INL vs Input Voltage,
C
IN
= 0.1µF, V
CC
= 5V, T
A
= 25°C
the voltage drop across R
S
due to the input current,
to the point that significant measurement errors exist.
Additionally, for some applications, increasing the R
S
• C
IN
product too much may unacceptably attenuate the signal
at frequencies of interest.
For most applications, it is desirable to implement C
IN
as
a high-quality 0.1µF ceramic capacitor and R
S
≤ 1k. This
capacitor should be located as close as possible to the
actual V
IN
package pin. Furthermore, the area encompassed
by this circuit path, as well as the path length, should be
minimized.
In the case of a 2-wire sensor that is not remotely
grounded, it is desirable to split R
S
and place series
resistors in the ADC input line as well as in the sensor
ground return line, which should be tied to the ADC GND
pin using a star connection topology.
Figure 10 shows the measured LTC2453 INL vs Input
Voltage as a function of R
S
value with an input capacitor
C
IN
= 0.1µF.
In some cases, R
S
can be increased above these guidelines.
The input current is zero when the ADC is either in sleep
or I/O modes. Thus, if the time constant of the input RC
circuit t = R
S
• C
IN
, is of the same order of magnitude or
longer than the time periods between actual conversions,
then one can consider the input current to be reduced
correspondingly.
Figure 11. Measured INL vs Input Voltage,
C
IN
= 0, V
CC
= 5V, T
A
= 25°C
APPLICATIONS INFORMATION
DIFFERENTIAL INPUT VOLTAGE (V)
–5
INL (LSB)
2
6
10
3
2453 F10
–2
–6
0
4
8
–4
–8
–10
–3–4
–1–2
1 2 4
0
5
R
S
= 10k
R
S
= 2k
R
S
= 1k
R
S
= 0
C
IN
= 0.1µF
V
CC
= 5V
T
A
= 25°C
DIFFERENTIAL INPUT VOLTAGE (V)
–5
INL (LSB)
2
6
10
3
2453 F11
–2
–6
0
4
8
–4
–8
–10
–3–4
–1–2
1 2 4
0
5
R
S
= 10k
R
S
= 1k, 2k
R
S
= 0
C
IN
= 0
V
CC
= 5V
T
A
= 25°C
