LTC2453
13
2453fc
INPUT SIGNAL FREQUENCY (MHz)
0
INPUT SIGNAL ATTENUATION (dB)
–40
0
1.00 1.25 1.50
2453 F12
–60
–80
–20
–100
2.5
5.0 7.5
INPUT SIGNAL FREQUENCY (Hz)
0
INPUT SIGNAL ATTENUATIOIN (dB)
–20
–10
0
480
2453 F13
–30
–40
–25
–15
–5
–35
–45
–50
12060
240180
360 420 540
300
600
Figure 12. LTC2453 Input Signal Attentuation vs Frequency Figure 13. LTC2453 Input Signal Attenuation
vs Frequency (Low Frequencies)
These considerations need to be balanced out by the input
signal bandwidth. The 3dB bandwidth ≈ 1/(2pR
S
C
IN
).
Finally, if the recommended choice for C
IN
is unacceptable
for the users specific application, an alternate strategy is
to eliminate C
IN
and minimize C
PAR
and R
S
. In practical
terms, this configuration corresponds to a low impedance
sensor directly connected to the ADC through minimum
length traces. Actual applications include current measure-
ments through low value sense resistors, temperature
meas urements, low impedance voltage source monitoring,
and so on. The resultant INL vs V
IN
is shown in Figure 11.
The measurements of Figure 11 include a capacitor C
PAR
corresponding to a minimum sized layout pad and a mini-
mum width input trace of about 1 inch length.
Signal Bandwidth, Transition Noise and Noise
Equivalent Input Bandwidth
The LTC2453 includes a sinc
1
type digital filter with the first
notch located at f
0
= 60Hz. As such, the 3dB input signal
bandwidth is 26.54Hz. The calculated LTC2453 input signal
attenuation vs frequency over a wide frequency range is
shown in Figure 12. The calculated LTC2453 input signal
attenuation vs frequency at low frequencies is shown in
Figure 13. The converter noise level is about 1.4µV
RMS
and can be modeled by a white noise source connected
at the input of a noise-free converter.
On a related note, the LTC2453 uses two separate A/D
converters to digitize the positive and negative inputs. Each
of these A/D converters has 1.4µV
RMS
transition noise.
If one of the input voltages is within this small transition
noise band, then the output will fluctuate one bit, regard-
less of the value of the other input voltage. If both of the
input voltages are within their transition noise bands, the
output can fluctuate 2 bits.
For a simple system noise analysis, the V
IN
drive circuit can
be modeled as a single-pole equivalent circuit character-
ized by a pole location f
i
and a noise spectral density n
i
.
If the converter has an unlimited bandwidth, or at least a
bandwidth substantially larger than f
i
, then the total noise
contribution of the external drive circuit would be:
V
n
= n
i
p / 2 f
i
Then, the total system noise level can be estimated as
the square root of the sum of (V
n
2
) and the square of the
LTC2453 noise floor (~1.4µV
2
).
APPLICATIONS INFORMATION
LTC2453
14
2453fc
TYPICAL APPLICATION
IN
+
7
8
R7
4.99k
1%
R6
4.99k
1%
2 1
3 4
9
IN
SCL
6
5
SDA
REF
C8
0.1µF
C7
0.1µF
C2
0.1µF
V
CC
R1
1k
E1
IN
+
E2
IN
R9
1k
C6
0.1µF
C3
1µF
C4
1µF
1
LT6660
3
42
R4
1.0Ω
C1
0.1µF
C10
0.1µF
JP1
EXT
5V
GND
REF
+
LTC2453
V
CC
V
CC
SCL SDA
GND
NC
3
14
12
9
10
11
5
7
4
6
2
1
V
+
J1
TO
CONTROLLER
V
CC
8 13
2453 TA02
EESCL
EEVCC
EESDA
EEGND
CS
SCK/SCL
MOSI/SDA
MISO
VUNREG
5V
GND GND
GND
E3
V
CC
E4
GND
E6
REF
JP2
EXT
GND
E5
REF
+
2
1
3
7
6
SDA
V
CC
4
8
5
SCL
WP
A2
A1
A0
GND
24LC025-I/ST
IN
V
+
OUT
GND GND
R8
4.99k
1%
C5
0.1µF
C9
1µF
DC1266A Demo Board Schematic
LTC2453
15
2453fc
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
PACKAGE DESCRIPTION
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
0.56 ± 0.05
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
2.15 ±0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
14
85
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0 – 0.05
(DDB8) DFN 0905 REV B
0.25 ± 0.05
0.50 BSC
PIN 1
R = 0.20 OR
0.25 × 45°
CHAMFER
0.25 ± 0.05
2.20 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.61
±
0.05
(2 SIDES)
1.15 ±0.05
0.70 ±0.05
2.55 ±0.05
PACKAGE
OUTLINE
0.50 BSC

LTC2453ITS8#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit 60Hz I2C Delta Sigma ADC
Lifecycle:
New from this manufacturer.
Delivery:
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