REV. B
AD1555/AD1556
–11–
AD1556 PIN FUNCTION DESCRIPTIONS (continued)
Pin No. Mnemonic Description
14 DOUT Serial Data Output. DOUT is used to access the conversion results or the contents of the Status
Register, depending on the logic state of the RSEL pin. At the beginning of a read operation, the
first data bit is output (MSB first). The data changes on the rising edge of SCLK and is valid on the
SCLK falling edge.
15 DRDY Data Ready. A logic high output indicates that data is ready to be accessed from the Output Data
Register. DRDY goes low once a read operation is complete. When selected, the DRDY output pin
has a type buffer that allows wired-OR connection of multiple AD1556s.
16 CS Chip Select. When set low the serial data interface pins DIN, DOUT, R/W, and SCLK are active; a
logic high disables these pins and sets the DOUT pin to Hi-Z.
17 R/W Read/Write. A read operation is initiated if R/W is high and CS is low. A low sets the DOUT pin to
Hi-Z and allows a write operation to the device via the DIN pin.
18 RSEL Register Select. When set high, the Conversion Data Register contents are output on a read opera-
tion. A low selects the Status Register.
19 DIN Serial Data Input. Used during a write operation. Loads the Configuration Register via the Input
Shift Register. Data is loaded MSB first and must be valid on the falling edge of SCLK.
20 ERROR Error Flag. A logic low output indicates an error condition occurred in the modulator or digital
filter. When ERROR goes low the ERROR bit in the status register is set high. The ERROR output
pin has an open drain type buffer with an internal 100 kΩ typical pull-up that allows wired-OR
connection of multiple AD1556s.
25 RESET Chip Reset. A logic high input clears any error condition in the status register and sets the configuration
register to the state of the corresponding hardware pins. On power-up, this reset state is entered.
26 PWRDN Power-Down Hardware Control. A logic high input powers down the filter. The convolution cycles
in the digital filter and the MCLK signal are stopped. All registers retain their data and the serial
data interface remains active. The power-down mode is entered on the first falling edge of CLKIN
after PWRDN is taken high. When exiting the power-down mode, a SYNC must be applied to
resume filter convolutions.
29 CSEL Filter Input Select. Selects the source for input to the digital filter. A logic high selects the TDATA
input, a low selects MDATA as the filter input.
30 TDATA Test Data. Input to digital filter for user test data.
31 SYNC Synchronization Input. The SYNC input clears the AD1556 filter in order to synchronize the start
of the filter convolutions. The SYNC event is initiated on the first CLKIN rising edge after the
SYNC pin goes high. The SYNC input can also be applied synchronously to the AD1556 decima-
tion rate without resetting the convolution cycles.
32 CLKIN Clock Input. The clock input signal, nominally 1.024 MHz, provides the necessary clock for the
AD1556. This clock frequency is divided by four to generate the MCLK signal for the AD1555.
35 MCLK Modulator Clock. Provides the modulator sampling clock frequency. The modulator always samples
at one-fourth the CLKIN frequency.
36 MDATA Modulator Data. This input receives the ones-density bit stream from the AD1555 for input to the
digital filter.
37 RESETD Decimator Reset. A logic high resets the decimator of the digital filter.
38 MFLG Modulator Error. The MFLG input is used to detect if an overrange condition occurred in the
modulator. Its logic level is sensed on the rising edge of CLKIN. When overrange condition
detected, ERROR goes low and updates the status register.
43–39 CB0–CB4 Modulator Control. These output control pins represent a portion of the data loaded into the AD1556
Configuration Register. CB0–CB2 are generally used to set the PGA gain or cause it to enter in the
PGA standby mode (Refer to Table III). CB3 and CB4 select the mux input voltage applied to the
PGA as described in Table III.
