AD1555BPZ Datasheet AD1556ASZ, AD1555APZ, AD1555BPZ | P19-P21

REV. B

AD1555/AD1556

–19–

DIGITAL FILTERING

The AD1556 is a digital finite impulse response (FIR) linear

phase low pass filter and serves as the decimation filter for the

AD1555. It takes the output bitstream of the AD1555, filters

and decimates it by a user-selectable choice of seven different

filters associated with seven decimation ratios, in power of 2

from 1/16 to 1/1024. With a nominal bit rate of 256 kbits/s at

the AD1556 input, the output word rate (the inverse of the

sampling rate) ranges from 16 kHz (1/16 ms) to 250 Hz (4 ms) in

powers of 2. The AD1556 filter achieves a maximum pass band

flatness of ±0.05 dB for each decimation ratio and an out-of-

band attenuation of –135 dB maximum for each decimation

ratio except 1/16 (OWR = 16 kHz) at which the out-of-band

attenuation is –86 dB maximum. Table II gives for each filter

the pass band frequency, the –3 dB frequency, the stop-band

frequency, and the group delay. The pass band frequency is 37.5%

of the output word rate, and the –3 dB frequency is approximately

41% of the output word rate. The noise generated by the AD1556,

even that due to the word truncation, has a negligible impact on

the dynamic range performance of the AD1555/AD1556 chipset.

Although dedicated to the AD1555, the AD1556 can also be

used as a very efficient and low power, low pass, digital filter of

a bitstream generated by other ⌺-⌬ modulators.

Architecture

The functional block diagram of the filter portion of the AD1556 is

given in Figure 10. The basic architecture is a two-stage filter.

The second stage has a decimation ratio of 4 for all filters except

at the output word rate of 250 Hz, where the decimation ratio is

8. Each filter is a linear phase equiripple FIR implemented by

summing symmetrical pairs of data samples and then convolut-

ing by multiplication and accumulation.

The input bitstream at 256 kHz enters the first filter and is

multiplied by the 26-bit wide coefficients tallied in Table IV.

Due to the symmetry of the filter, only half of the coefficients

are stored in the internal ROM and each is used twice per con-

volution. Because the multiplication uses a 1-bit input data, the

convolution for the first stage is implemented with a single accu-

mulator 29-bits wide to avoid any truncation in the accumulation

process. The output of the first-stage filter is decimated with the

ratios given in Table IV and then are stored in an internal RAM

which truncates the accumulator result to 24 bits.

The second-stage filter architecture is similar to the first stage.

The main difference is the use of a true multiplier. The multiplier,

the accumulator, and the output register, which are respectively

32-bits, 35-bits and 24-bits wide, introduce some truncation

that does not affect the overall dynamic performance of the

AD1555/AD1556 chipset.

Filter Coefficients

As indicated before, each stage for each filter uses a different

set of coefficients. These coefficients are provided with the

EVAL-AD1555/AD1556EB, the evaluation board for the

AD1555 and the AD1556.

Table IV. Filter Definition

Output Word Rate F

(Hz) Decimation Ratio Number of Coefficients

(Sampling Rate [ms]) First Stage Second Stage First Stage Second Stage

16000 [1/16 ms] 4 4 32 118

8000 [1/8 ms] 8 4 64 184

4000 [1/4 ms] 16 4 128 184

2000 [1/2 ms] 32 4 256 184

1000 [1 ms] 64 4 512 184

500 [2 ms] 128 4 1024 184

250 [4 ms] 128 8 1024 364

FIRST-STAGE FILTER

INPUT DATA STORAGE

MODULATOR BITSTREAM

1-BIT WIDE AT 256kbits/s

FIRST-STAGE

FILTER 29-BIT

ACCUMULATOR

MULTIPLIER

35-BIT

ACCUMULATOR

RAM 1024

BY 1 BIT

FIRST-STAGE

FILTER

COEFFICIENTS

ROM 1008 BY 26 BITS

RAM 364 BY 24 BITS

ROM 333 BY 26 BITS

SECOND-STAGE

FILTER INPUT

DATA STORAGE

SECOND-STAGE

FILTER INPUT

COEFFICIENTS

SECOND-STAGE FILTER

124

24 32

Figure 10. AD1556 Filter Functional Block Diagram

REV. B

AD1555/AD1556

–20–

RESET Operation

The RESET pin initializes the AD1556 in a known state.

RESET is active on the next CLKIN rising edge after the

RESET input is brought high as shown in Figure 4. The reset

value of each bit of the configuration and the status registers are

indicated in Table V and Table VIII. The filter memories are

not cleared by the reset. Filter convolutions begin on the next

CLKIN rising edge after the RESET input is returned low. A

RESET operation is done on power-up, independent of the

RESET pin state.

In multiple ADCs applications where absolute synchroniza-

tion—even below the noise floor—is required, RESETD, which

resets the decimator, can be tied to RESET to ensure this

synchronization.

Power-Down Operation

The PWRDN pin puts the AD1556 in a power-down state.

PWRDN is active on the next CLKIN rising edge after the

PWRDN input is brought high. While in this state, MCLK is

held at a fixed level and the AD1555 is therefore powered

down too. The serial interface remains active allowing read and

write operations of the AD1556. The configuration and status

registers maintain their content during the power-down state.

SYNC Operation

SYNC is used to create a relationship between the analog input

signal and the output samples of the AD1556. The SYNC event

does two things:

•

It synchronizes the AD1555 clock, MCLK, to the AD1556

clock, CLKIN, as shown in Figure 3.

•

It clears the filter and then initiates the filter convolution.

Exactly one sampling rate delay later, the DRDY pin goes

high.

A SYNC event occurs on the next CLKIN rising edge

after the SYNC input is brought high as shown in Figure 3.

The DRDY output goes high on the next falling edge of

CLKIN. SYNC may be applied once or kept high, or applied

synchronously at the output word rate, all with the same effect.

Configuring and Interfacing the AD1556

The AD1556 configuration can be loaded either by hardware

(H/S pin high) or via the serial interface of the AD1556 (H/S

pin low). To operate with the AD1556, the CLKIN clock must be

kept running at the nominal frequency of 1.024 MHz. Table V

gives the description of each bit of the configuration register and

Table VI defines the selection of the filter bandwidth.

When the

software mode is selected (H/S pin low), the configuration register

is loaded using the pins DIN, SCLK, CS, and R/W. In this mode,

when RESET is active, the configuration register mimics the selec-

tion of the hardware pins. The AD1556 and the AD1555 can be

put in power-down by software.

The DRDYBUF bit controls the operating mode of the DRDY

output pin. When the DRDYBUF bit is low, the DRDY is a con-

ventional CMOS push-pull output buffer as shown in Figure 11.

When the DRDYBUF bit is high, the DRDY output pin is an

open drain PMOS pull-up as shown in Figure 11. Many DRDY

pins may be connected with an external pull-down resistor in a

wired OR to minimize the interconnection between the AD1556s

and the microprocessor in multichannel applications. The DRDY

pin is protected against bit contention.

By connecting DRDY to RSEL directly, and applying 48 SCLK

cycles, both data and status can be read sequentially, data

Table VI. Filter Bandwidth Selection

BW2 BW1 BW0 Output Rate (ms)

00 0 4

00 1 2

01 0 1

01 1 1/2

10 0 1/4

10 1 1/8

11 0 1/16

11 1Reserved

Table V. Configuration Register Data Bits

Bit

Number Name Description RESET State

DB15 (MSB) X X

DB14 X X

DB13 X X

DB12 X X

DB11 PWRDN Power-Down Mode PWRDN

DB10 CSEL Select TDATA Input CSEL

DB9 X X

DB8 BW2 Filter Bandwidth Selection BW2

DB7 BW1 Filter Bandwidth Selection BW1

DB6 BW0 Filter Bandwidth Selection BW0

DB5 DRDYBUF DRDY Output Mode 0 (Push-Pull)

DB4 CB4 PGA Input Select PGA4

DB3 CB3 PGA Input Select PGA3

DB2 CB2 PGA Gain Select PGA2

DB1 CB1 PGA Gain Select PGA1

DB0 (LSB) CB0 PGA Gain Select PGA0

REV. B

AD1555/AD1556

–21–

AD1556

DGND

DRDY

DRDYBUF = 0 DRDYBUF = 1

TO THE

MICROPROCESSOR

AD1556

DRDY

TO THE

MICROPROCESSOR

TO OTHER

AD1556s

AD1556

DRDY

DGND

Figure 11. DRDY Output Pin Configuration

Analog Input and Digital Output Data Format

When operating with a nominal MCLK frequency of 256 kHz,

the AD1555 is designed to output a ones-density bitstream from

0.166 to 0.834 on its MDATA output pin corresponding to an

input voltage from –2.25 V to +2.25 V on the MODIN pin.

The AD1556 computes a 24-bit two’s complement output whose

codes range from decimal –6,291,456 to +6,291,455 as shown

in Table VII.

Table VII. Output Coding

Analog Input Output Code

MODIN Hexa Decimal

~ +2.526 V* 5FFFFF +6291455

~ +2.25 V 558105 +5603589

~ +2 V 4C00E8 +4980968

~ 0 V 000000 0

~ –2 V B3FF17 –4980969

~ –2.25 V AA7EFA –5603590

~ –2.526 V* A00000 –6291456

*Input out of range.

STATUS Register

The AD1556 status register contains 24 bits that capture poten-

tial error conditions and readback the configuration settings.

The status register mapping is defined in Table VIII.

The ERROR bit is the logical OR of the other error bits, OVWR,

MFLG, and ACC. ERROR and the other error bits are reset

low after completing a status register read operation or upon

RESET. The ERROR bit is the inverse of the ERROR output pin.

The OVWR bit indicates if an unread conversion result is over-

written in the output data register. If a data read was started but

not completed when new data is loaded into the output data

The MFLG status bit is set to the state of the MFLG input pin

on the rising edge of CLKIN. MFLG will remain set high as long

as the MFLG bit is set. The MFLG status bit will not change

during power-down or RESET.

The ACC bit is set high and the data output is clipped to either

+FS (0111 . . . ) or –FS (1000 . . . ) if an underflow or overflow

has occurred in the digital filter.

The FLSTL bit indicates the digital filter has settled and the

conversion results are an accurate representation of the analog

input. FLSTL is set low on RESET, at power-up, and upon

exiting the power-down state. FLSTL also goes low when SYNC

sets the start of the filter’s convolution cycle, when changes are

made to the device setting with the hardware pins CB0–CB4,

BW0–BW2, or CSEL, and when the MFLG status bit is set

high. When FLSTL is low the OVWR, MFLG, ACC, and DRNG

status bits will not change.

The DRNG bit is used to indicate if the analog input to the

AD1555 is outside its specified operating range. The DRNG bit

is set high whenever the AD1556 digital filter computes four

consecutive output samples that are greater than decimal

+6,291455 or all less than –6,291456.

Layout

The AD1555 has very good immunity to noise on the power

supplies. However, care should still be taken with regard to

grounding layout.

The printed circuit board that houses the AD1555 and the

AD1556 should be designed so the analog and digital sections

are separated and confined to certain areas of the board. This

facilitates the use of ground planes that can be easily separated.

Digital and analog ground planes should be joined in only one

place, preferably underneath the AD1555, or at least as close as

possible to the AD1555. If the AD1555 is in a system where

multiple devices require analog-to-digital ground connections,

the connection should still be made at one point only, a star

ground point, which should be established as close as possible to

the AD1555.

It is recommended to avoid running digital lines under the

device since these will couple noise onto the die. The analog

ground plane should be allowed to run under the AD1555 to

avoid noise coupling. Fast switching signals such as MDATA and

MCLK should be shielded with digital ground to avoid radiating

noise to other sections of the board and should never run near

analog signal paths. Crossover of digital and analog signals

should be avoided. Traces on different but close layers of the

board should run at right angles to each other. This will re-

duce the effect of feedthrough through the board.

The power supply lines to the AD1555 should use as large a

trace as possible to provide low impedance paths and reduce

the effect of glitches on the power supply lines. Good decoupling

is also important to lower the supplies impedance resent to the

AD1555 and reduce the magnitude of the supply spikes. Decou-

pling ceramic capacitors, typically 100 nF, should be placed on

power supply pins +V

, –V

, and V

close to, and ideally right

up against these pins and their corresponding ground pins.

Additionally, low ESR 10 µF capacitors should be located in

the vicinity of the ADC to further reduce low frequency ripple.

The V

supply of the AD1555 can either be a separate supply

or come from the analog supply V

. When the system digital

supply is noisy, or fast switching digital signals are present, it is

recommended, if no separate supply is available, to connect the

digital supply to the analog supply V

through an RC filter

as shown in Figure 7.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

AD1555BPZ

Mfr. #:

Buy AD1555BPZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC IC 256 ksps w/PGA

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD1555BPZ

AD1555BPZ

Products related to this Datasheet