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LTC4125EUFD#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
LTC4125
22
4125f
For more information www.linear.com/LTC4125
coupling condition, this exit point also coincides with a
voltage step at the feedback pin that is larger than all the
earlier voltage steps.
Note that Optimum Power Search only deems this condition
of ∆V
FB
>V
DTH
valid when it follows a step where ∆V
FB
is less than V
IN
/64. In the example shown in Figure16,
∆V
FB
immediately preceding the optimum point is 24mV,
and ∆V
FB
at the optimum point is 432mV.
In order to detect the optimum point in this example, the
DTH pin needs to be programmed for a particular threshold
(less than 432mV) to allow the ∆V
FB
>V
DTH
exit condition.
The DTH threshold is programmed with a resistor divider
between V
IN
and GND as follows:
V
DTH
=
R
DTH2
R
DTH1
+R
DTH2
• V
IN
The FB pin voltage is sampled with an internal 7-bit A/D,
and the DTH pin comparator is also quantized to 7 bits
with both sharing a full input range of GND to V
IN
. There-
fore, the ∆V
FB
>V
DTH
exit condition is subject to a 7-bit
quantization or rounding error.
In this example, with V
IN
=5V, the LSB of the 7-bit A/D
is 39mV. Therefore, 432mV of V
FB
step gives 11.08 bits.
DELTA THRESHOLD (DTH PIN)
One of the exit conditions in the Optimum Power Search
algorithm is when the increase in the feedback voltage
(V
FB
) at any particular step during the sweep is larger than
V
DTH
. In a typical sweep such as shown by the voltage
steps in Figure14, multiple exit conditions implemented
by the LTC4125 to detect the optimum transmit power are
satisfied. Therefore the DTH programmable exit condition
is not required. However, some situations may benefit
from using DTH.
In the example circuit of Figure7, the V
DTH
exit condition
is useful in order to find the optimum power when the
LTC4120 receiver circuit has the lowest output power at
the highest target separation (lowest coupling). Figure16
shows an example of voltage stepping at the feedback
pin when the LTC4120 is charging a single cell Li-Ion
battery in trickle charge constant current mode at 40mA
(V
BAT
=2.7V), at a 10mm distance. The dotted lines show
the stepping at the FB and PTH pins when DTH is left open,
and the second graph shows the stepping at the same pins
when DTH is programmed appropriately.
In this particular example, the desired optimum power
point corresponds to when I
CHG
at the receiver is regu-
lated at its desired target of 40mA. In this low load, low
applicaTions inForMaTion
TIME (s)
0.0
VOLTAGE (V)
I
CHG
AT RX (mA)
42.0
35.0
21.0
7.0
28.0
14.0
0.0
3.0
2.5
1.5
0.5
2.0
1.0
0.0
0.400.20
4125 F16
0.500.300.100.05 0.25 0.350.15 0.45
∆V
FB
I
CHG
AT RX
V
PTH
WITH DTH
V
FB
WITH DTH
V
FB
WITHOUT DTH
V
PTH
WITHOUT DTH
Figure16. V
FB
Voltage Stepping During A Sweep with LTC4120 in
Trickle Charge CC Mode as the Receiver Circuit at 10mm Spacing
LTC4125
23
4125f
For more information www.linear.com/LTC4125
As a quick rule of thumb, changing the value of R
NTC1
to
be smaller relative to R
NTC2
at 25°C will move the tem-
perature threshold higher and vice versa. For example,
using a Vishay “
Curve 2” thermistor whose nominal value
at 25°C is 10kΩ, the user can set the temperature to be at
50°C by setting the value of R
NTC1
=7.5kΩ.
Leaving the NTC pin open or connecting it to a capacitor
disables all NTC overtemperature fault functionality.
LTC4120 EFFICIENCY OPTIMIZER USING DHC
When using the LTC4125 in a wireless power system
with the LTC4120, the DHC pin on the LTC4120 can be
configured to further optimize the overall efficiency of the
system (see Figure7—circuit enclosed with dotted lines).
Instead of driving a capacitor, the DHC pin turns on a 15V
clamp circuit (D
C
, R
C
, M1) on the rectified input voltage
of the receiver circuit. Note that under some worst case
transient conditions, the 15V clamp needs to dissipate
up to 0.8W.
The 15V clamp voltage is selected to provide 1V margin
to the LTC4120 14V DHC pin threshold. The RC network
value connected to the DHC pin is selected to provide
enough delay to allow the input voltage on the LTC4120
to rise to 39V (allowing for optimum power detection on
the LTC4125) before the 15V clamp is activated. The fol
-
lowing criteria should be followed:
RC
V
ZH
– V
BE
( )
> 1.5 • T2
Where T2 is the settling time of the optimum power search
step discussed in the Timer Capacitors section. In Figure7,
V
ZH
=39V, V
BE
=0.7V and T2 is 18ms. Therefore, the value
of RC needs to be greater than 1s. Note that the resistance
value is chosen such that at the 15V clamp voltage, the
NPN base current supplied through the resistor is greater
than 0.5mA. Therefore, select 24.9k for R and 47µF for C.
The most important criteria for the NPN is that the common-
emitter current gain at I
b
=0.5mA is greater than 50, and
its maximum power dissipation capability is greater than
0.5W. A standard 3904 NPN works well.
Set the V
DTH
value to 9.4 bits=367mV, such that at this
desired step the ∆V
FB
>V
DTH
condition is satisfied. With
V
IN
=5V, and a recommended R
DTH1
+R
DTH2
value in
the order of 100kΩ, the following values are obtained:
R
DTH2
=7.87kΩ and R
DTH1
=100kΩ.
OVER TEMPERATURE FAULT THRESHOLD
One of the fault conditions used in the Optimum Power
Search is the overtemperature fault. To set this temperature
fault threshold, connect an NTC thermistor R
NTC2
, between
the NTC pin and the GND pin, and a resistor R
NTC1
, from the
IN pin to the NTC pin (Figure17). In a typical application,
the NTC thermistor is thermally coupled to the surface of
the transmitting coil, and the temperature threshold is set
to ensure safe temperature on the coil surface.
In the simplest application, R
NTC1
is a 1% resistor with a
value equal to the value of the chosen NTC thermistor at
25°C (R
NTC2
at 25°C). In this simple setup, the LTC4125
senses a fault condition when the resistance of the NTC
thermistor drops to 0.538 times the value of R
NTC2
at
25°C. For a Vishay “Curve 2” thermistor (B
25
/B
85
=3486),
this corresponds to approximately 41.5°C. With a Vishay
“Curve 2” thermistor, the LTC4125 has approximately 5°C
of hysteresis to prevent oscillation about the trip point.
R
NTC2
R
NTC1
IN
NTC
LTC4125
4125 F17
Figure17. NTC Thermistor Connection
Consult manufacturer data sheets for other types of NTC
thermistors. The temperature threshold can be adjusted
by changing the value of R
NTC1
. Instead of simply setting
R
NTC1
to be equal to R
NTC2
at 25°C, R
NTC1
is set according
to the following formulas:
R
NTC1
= 1.857 • R
NTC2
at temperature_threshold
applicaTions inForMaTion
LTC4125
24
4125f
For more information www.linear.com/LTC4125
BOARD LAYOUT CONSIDERATIONS
When using an LTC4125 circuit, care must be taken when
handling the board since high voltage is generated in
the resonant LC tank. Figure18 indicates in red the high
voltage nodes that are present in a typical circuit. With
careful layout the area of these high voltage nodes should
be minimized and isolated for safe and simple operation.
For accurate sensing of the input current, the sense lines
from R
IS
must use proper Kelvin connections all the way
back to the sense resistor terminals as shown in Figure18.
The lines connected to these resistors must be routed close
together (the loop area between the sense traces should be
kept to a minimum) and away from noise sources (such
as the transmit coil) to minimize error. The gain resistor
R
IN
and filtering capacitor C
IF
should be placed close to
the LTC4125, so that the filtered high impedance lines do
not need to travel far before reaching the IS
+
and IS
–
pins.
The decoupling capacitors C
IN
, C
IN1
and C
IN2
must be
placed as close to the LTC4125 as possible. This allows
as short a route as possible (minimized inductance) from
these capacitors to the respective IN pins and the GND pins
of the part. Figure18 indicates in blue and green the hot
current loops flowing through C
IN1
, IN1, SW1 and GND;
as well as through C
IN2
, IN2, SW2 and GND. The physi-
cal layout of these hot current loops should be made as
small as possible to minimize parasitic resistance as well
as inductance in the loop.
Although the inductance of the
trace between the LTC4125 and the transmit coil does not
matter, the resistance does. Use a trace that is the shortest,
and has maximum available copper thickness and width.
Last but not least, the amount of current flowing in the
transmit coil can be significant. This current also flows
through the switches in the LTC4125. For an applica
-
tion with a high quality factor transmit coil and resonant
capacitor, it is not rare to have current upward of 2.5A
RMS. At 2.5A, the power dissipation in the LTC4125 is
approximately 1.25W (in a full bridge setup, the current
always flows through two switches ~ 0.2Ω). With a θ
JA
of 43°C/W, the LTC4125 part will operate at roughly 55°C
above ambient temperature.
In order to ensure that these quoted thermal resistance
numbers are realized, the following good layout practices
should be followed: use the maximum copper weight in
the board layers as practically and economically possible,
place the recommended number of vias connected to the
exposed pad of the part (refer to LTC Application Notes
for thermal enhanced leaded plastic packages available
at www.linear.com), and use the maximum size of GND
plane connected to these vias. For proper operation of the
LTC4125, ensure that other common good board layout
practices are also followed. These include isolating noisy
power and signal grounds, having a good low impedance
C
IF
C
IN1
C
IN2
R
IN
R
IS
R
FB1
C
IN
R
FB2
LTC4125
4125 F18
IS
+
IS
–
IN IN1 IN2
SW1FB SW2
GND
(PIN 21)
C
TX
C
FB1
L
TX
A B C D
I
IN1
CURRENT LOOP:
IN1→SW1→ LC→ SW2→ GND→ C
IN1
I
IN2
CURRENT LOOP:
IN2→SW2→ LC→ SW1→ GND→ C
IN2
Figure18. High Voltage Nodes (Red), Kelvin Lines and Hot Current Loops in the LTC4125 Circuit
applicaTions inForMaTion
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LTC4125EUFD#PBF

Mfr. #:
Buy LTC4125EUFD#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Wireless Charging ICs 5W AutoResonant Wireless Pwr Transmitter
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