M5253DEMO Datasheet M5253DEMO | P4-P6

M5253 Demo Board User Manual, Rev. 0

Hardware Submodules

Freescale Semiconductor4

3 Hardware Submodules

This section describes the major sections of the M5253 demo board.

3.1 Processor

The MCF5253 processor is the fundamental control chip on the M5253 demo board. This is a

version 2 (V2) ColdFire processor running at a maximum core speed of 140 MHz. MCF5253 implements

an 8 KB instruction cache, three UART channels, two timers, 128 KB of SRAM, a QSPI (queued serial

peripheral interface) module, two I

C modules, three I

S modules, an IDE module, a dedicated ATA

interface with DMA support, two FlexCAN modules, an OTG USB 2.0 controller with integrated physical

interface, real-time clock (RTC), a flash memory stick interface, 60 parallel I/O ports (which are

multiplexed with other signals), and the system integration module (SIM). All of the core-processor

registers are 32 bits wide except for the status register (SR) which is 16 bits wide. This processor

communicates with the external devices over a 16 bits wide data bus, D[31:16]. The processor has a logic

to generate up to four chip selects, and support for a bank of SDRAMs. This board has brought out almost

every silicon feature for evaluation and developing the customer design.

3.2 Resets

The system reset signal is coming from the power management IC MC34702 with a reset button. The reset

signal feeds the CPU, flash, BDM, and DM9000 devices. This signal also appears on the connector J17 for

external use.

3.3 System Clock

This board uses a 11.2896 MHz crystal for the system main clock input CRIN.

The system PLL output-clock equation is as follows:

Eqn. 1

Following table is the clock configuration:

Here is the example code to configure the system running at 140 MHz:

Table 2. System Clock Configuration

Fin (MHz) CPUDIV CRSEL VCXODIV PLLDIV VCXOOUT PSTCLK (MHz)

11.2896 2 0 62 5 1 140 (default)

11.2896 2 0 42 4 1 120

11.2896 3 0 51 4 1 96

11.2896 4 0 51 4 1 72

PSTCLK =

VCXOOUTCPUDIVPLLDIV

VCXO DIV

Fin

∗

Hardware Submodules

M5253 Demo Board User Manual, Rev. 0

Freescale Semiconductor 5

…

MCF_CLOCK_PLLCONFIG = 0x1243E054;

MCF_CLOCK_PLLCONFIG = 0x1243E055;

/* Wait for PLL to lock */

while (!(MCF_CLOCK_PLLCONFIG & MCF_CLOCK_PLLCONFIG_LOCK))

;

…

Audio module also uses the 11.2896 MHz frequency for operation, so Faudio = AUDIOCLK = CRIN

(A20/A24 switch pull up, down).

3.4 Booting and Programming the Flash/EEPROM Memory

This demo board includes both a serial boot EEPROM and the program flash memories on-board.

3.4.1 Serial Boot EEPROM

The serial boot EEPROM (AT24C256) can store configuration parameters and the boot code. It is I

C bus

EEPROM and the address is 1010000x (x means R/W#-bit).

When the MCF5253 boot mode is configured as I

C master boot (A23 pull down and GPIO50 = 0,

GPIO49 = 0, GPIO48 = 0) the MCF5253 loads the boot code from the I

C EEPROM at powerup. The

board uses this EEPROM just for a demonstration of the MCF5253’s serial-boot function. There is no

pre-flashed software inside the EEPROM. Customer can put his own boot code there and configure the

data into this device. Please see Table 4 for more details about the serial-boot configuration.

3.4.2 Flash

A 8 MB (4Mx16) flash (SST39VF6401) memory resides on the CS0 space of the FlexBus memory on the

demo board. The software must configure the memory-access parameters to be consistent with the

hardware configuration. The SST39VF6401 is uniformed as 2 Kword sectors, totally in 2 K sectors.

When the MCF5253 boot mode is configured as CS0/CS4 boot (A23 pullup), the CPU loads the code from

the flash at powerup. We intended to reside the dBUG or U-boot as the bootloader at the beginning of the

flash memory.

The CS0 initialization code is below:

…

; CS0 = Flash SST39VF6401B - 8Mbytes

writemem.w 0x10000080 0xFF80 ; CSAR0 - FlashBase = 0xFF80_0000 - 0xFFFF_FFFF

writemem.w 0x1000008A 0x0D80 ; CSCR0

writemem.l 0x10000084 0x007F0021 ; CSMR0 - 0xFF80_0000 - 0xFFFF_FFFF

…

Flash address

0xFF80_0000 ~ 0xFFFF_FFFF

M5253 Demo Board User Manual, Rev. 0

Hardware Submodules

Freescale Semiconductor6

3.5 SDRAM Interface

The M5253 demo board provides 16 MB of on-board SDRAM, which is located at 0x0. The on-board

terminations are provided. The software should take notice of the timing configuration of this device for

the SDRAM controller module.

The SDRAM timing characters are listed below:

tRCD > 20 ns

CASL = 2 CLK

45 ns < tRAS < 100 ns

tRP > 20 ns

tRWL, RDL = 1 CLK (less than 100 MHz speed)

Here is the initialization code example for the SDRAM controller:

…

; set up 5253 cpu settings

; initialize memory settings SDRAM base Address 0x0000_0000

writemem.w 0x10000100 0x8209 ;SDRAM0 DCR0A

writemem.l 0x10000108 0x00002320 ;SDRAM0 DACR0A

writemem.l 0x1000010C 0x00FC0001 ;SDRAM0 DMR0A

writemem.l 0x10000108 0x00002328 ;SDRAM0 DACR0B

writemem.l 0x00000000 0x00000000 ;SDRAM0 MEMWR0

writemem.l 0x10000108 0x0000A320 ;SDRAM0 DACR0C

writemem.l 0x10000108 0x0000A360 ;SDRAM0 DACR0D

writemem.l 0x00000800 0x00000800 ;SDRAM0 MODE0…

3.6 BDM Interfaces — Processor

The M5253 demo board provides an on-board BDM (background debug mode) module and a connector

(26-pin header) to give the final user the ability to utilize the BDM features of the MCF5253 processor.

With the on-board BDM, the customer can use a USB A-to-B cable for debugging and downloading the

software. The 26-pin header is not populated on the board by default, the customer can populate it on the

J14. To enable the header, the customer also needs to populate four 0 Ω resistors on R4 to R7.

3.7 USB 2.0 OTG

The MCF5253 processor contains a USB high-speed OTG module. This module is USB 2.0 compliant. It

supports both the host and the device modes, and provides an on-chip high-speed/full-speed/low-speed

transceiver. One mini-AB receptacle (USB 2.0 OTG) is provided on the Jamaica board. The board also

provides an external power distribution switch (MIC2026) to provide the VBUS when necessary. The USB

module uses a 24 MHz crystal for module clock.

SDRAM address

0x0000_0000 ~ 0x00FF_FFFF

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

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