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ATMEGA128-16MU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
19
2467XS–AVR–06/11
ATmega128
Rev. 2467N-03/06 1. Updated note for Figure 1 on page 2.
2. Updated “Alternate Functions of Port D” on page 77.
3. Updated “Alternate Functions of Port G” on page 84.
4. Updated “Phase Correct PWM Mode” on page 100.
5. Updated Table 59 on page 133, Table 60 on page 133.
6. Updated “Bit 2 – TOV3: Timer/Counter3, Overflow Flag” on page 141.
7. Updated “Serial Peripheral Interface – SPI” on page 162.
8. Updated Features in “Analog to Digital Converter” on page 230
9. Added note in “Input Channel and Gain Selections” on page 243.
10. Updated “Errata” on page 15.
Rev. 2467M-11/04 1. Removed “analog ground”, replaced by “ground”.
2. Updated Table 11 on page 40, Table 114 on page 285, Table 128 on page 303, and
Table 132 on page 321. Updated Figure 114 on page 238.
3. Added note to “Port C (PC7..PC0)” on page 6.
4. Updated “Ordering Information” on page 12.
Rev. 2467L-05/04 1. Removed “Preliminary” and “TBD” from the datasheet, replaced occurrences of ICx
with ICPx.
2. Updated Table 8 on page 38, Table 19 on page 50, Table 22 on page 56, Table 96 on
page 242, Table 126 on page 299, Table 128 on page 303, Table 132 on page 321, and
Table 134 on page 323.
3. Updated “External Memory Interface” on page 25.
4. Updated “Device Identification Register” on page 253.
5. Updated “Electrical Characteristics” on page 318.
6. Updated “ADC Characteristics” on page 325.
7. Updated “Typical Characteristics” on page 333.
8. Updated “Ordering Information” on page 12.
Rev. 2467K-03/04 1. Updated “Errata” on page 15.
20
2467XS–AVR–06/11
ATmega128
Rev. 2467J-12/03 1. Updated “Calibrated Internal RC Oscillator” on page 41.
Rev. 2467I-09/03 1. Updated note in “XTAL Divide Control Register – XDIV” on page 36.
2. Updated “JTAG Interface and On-chip Debug System” on page 48.
3. Updated values for V
BOT
(BODLEVEL = 1) in Table 19 on page 50.
4. Updated “Test Access Port – TAP” on page 246 regarding JTAGEN.
5. Updated description for the JTD bit on page 255.
6. Added a note regarding JTAGEN fuse to Table 118 on page 288.
7. Updated R
PU
values in “DC Characteristics” on page 318.
8. Added a proposal for solving problems regarding the JTAG instruction IDCODE in
“Errata” on page 15.
Rev. 2467H-02/03 1. Corrected the names of the two Prescaler bits in the SFIOR Register.
2. Added Chip Erase as a first step under “Programming the Flash” on page 315 and
“Programming the EEPROM” on page 316.
3. Removed reference to the “Multipurpose Oscillator” application note and the “32kHz
Crystal Oscillator” application note, which do not exist.
4. Corrected OCn waveforms in Figure 52 on page 125.
5. Various minor Timer1 corrections.
6. Added information about PWM symmetry for Timer0 and Timer2.
7. Various minor TWI corrections.
8. Added reference to Table 124 on page 291 from both SPI Serial Programming and Self
Programming to inform about the Flash Page size.
9. Added note under “Filling the Temporary Buffer (Page Loading)” on page 280 about
writing to the EEPROM during an SPM Page load.
10. Removed ADHSM completely.
11. Added section “EEPROM Write During Power-down Sleep Mode” on page 24.
12. Updated drawings in “Packaging Information” on page 13.
Rev. 2467G-09/02 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
Rev. 2467F-09/02 1. Added 64-pad QFN/MLF Package and updated “Ordering Information” on page 12.
21
2467XS–AVR–06/11
ATmega128
2. Added the section “Using all Locations of External Memory Smaller than 64 Kbyte”
on page 32.
3. Added the section “Default Clock Source” on page 37.
4. Renamed SPMCR to SPMCSR in entire document.
5. When using external clock there are some limitations regards to change of frequency.
This is descried in “External Clock” on page 42 and Table 131, “External Clock
Drive,” on page 320.
6. Added a sub section regarding OCD-system and power consumption in the section
“Minimizing Power Consumption” on page 47.
7. Corrected typo (WGM-bit setting) for:
“Fast PWM Mode” on page 98 (Timer/Counter0).
“Phase Correct PW M Mode” on page 100 (Timer/Counter0).
“Fast PWM Mode” on page 151 (Timer/Counter2).
“Phase Correct PW M Mode” on page 152 (Timer/Counter2).
8. Corrected Table 81 on page 191 (USART).
9. Corrected Table 102 on page 259 (Boundary-Scan)
10. Updated Vil parameter in “DC Characteristics” on page 318.
Rev. 2467E-04/02 1. Updated the Characterization Data in Section “Typical Characteristics” on page 333.
2. Updated the following tables:
Table 19 on page 50, Table 20 on page 54, Table 68 on page 157, Table 102 on page 259,
and Table 136 on page 328.
3. Updated Description of OSCCAL Calibration Byte.
In the data sheet, it was not explained how to take advantage of the calibration bytes for
2MHz, 4MHz, and 8MHz Oscillator selections. This is now added in the following sections:
Improved description of “Oscillator Calibration Register – OSCCAL” on page 41 and “Cali-
bration Byte” on page 289.
Rev. 2467D-03/02 1. Added more information about “ATmega103 Compatibility Mode” on page 5.
2. Updated Table 2, “EEPROM Programming Time,” on page 22.
3. Updated typical Start-up Time in Table 7 on page 37, Table 9 and Table 10 on page 39,
Table 12 on page 40, Table 14 on page 41, and Table 16 on page 42.
4. Updated Table 22 on page 56 with typical WDT Time-out.
5. Corrected description of ADSC bit in “ADC Control and Status Register A – ADCSRA”
on page 244.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ATMEGA128-16MU

Mfr. #:
Buy ATMEGA128-16MU
Manufacturer:
Microchip Technology / Atmel
Description:
8-bit Microcontrollers - MCU 128kB Flash 4kB EEPROM 53 I/O Pins
Lifecycle:
New from this manufacturer.
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