MAX1954A
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
16 ______________________________________________________________________________________
The error-amplifier gain at f
C
is:
R
C
is then calculated as:
C
C
and C
f
can then be calculated as:
Applications Information
See Table 2 for suggested manufacturers of the com-
ponents used with the MAX1954A.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention.
Follow these guidelines for good PC board layout:
1) Place IC decoupling capacitors as close as possible
to IC pins. Keep separate the power-ground plane
(connected to pin 7) and the signal-ground plane
(connected to pin 4). The IN pin has two decoupling
capacitors. One connects to pin 7 and one connects
to pin 4.
2) Place the MOSFETs’ decoupling capacitors as
close as possible and place them directly across
from the high-side MOSFET drain and the low-side
MOSFET source.
3) Input and output capacitors are connected to the
power-ground plane; all other capacitors are con-
nected to the signal-ground plane.
4) Keep the high-current paths as short as possible.
5) Connect the drain leads of the power MOSFET to a
large copper area to help cool the device. Refer to
the power MOSFET data sheet for recommended
copper area.
6) Connect HSD directly to the drain leads of the high-
side MOSFET.
7) Connect LX directly to the drain of the low-side
MOSFET.
8) Place the low-side MOSFET so that its source is as
close as possible to pin 7.
9) Ensure all feedback connections are short and
direct. Place the feedback resistors as close as
possible to the IC.
10) Route high-speed switching nodes away from sen-
sitive analog areas (FB, COMP).
11)The trace length from the gates of the low-side and
high-side MOSFETs to DH and DL should be no
longer than 700 mils.
To aid design, a sample layout is available in the
MAX1954A evaluation kit.
