PCA9522 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 28 September 2011 8 of 20
NXP Semiconductors
PCA9522
Fast dual bidirectional bus buffer with hot insertion logic
10. Application information
10.1 Design considerations
Figure 7 shows a typical application for the PCA9522. The IC can level shift between
various bus voltages, without the need for additional external components. Higher bus
voltages and currents outside the range of the standard I
2
C-bus specification can be
catered for, providing a longer range capability and higher noise immunity.
The enable pin (EN) can be used to interface buses of different operating frequencies.
When enabled, the bus frequency is limited to the maximum 100 kHz of the slave device.
When disabled, the slave is isolated, and the remaining bus can be run at 400 kHz. The
timing performance and current sinking capability will allow it to run well in excess of the
400 kHz maximum limit of the Fast-mode I
2
C-bus.
Figure 8 shows the PCA9522 used in a backplane application. Peripheral cards and
backplanes operating at a range of voltages can be interfaced together using a minimum
of components. In this example, cards are running at 1.8 V and 3.3 V, while the backplane
is at 5 V. Cards operating buses between 1.8 V and 10 V can be catered for in the same
system.
Each card can be safely isolated from the system by disabling the PCA9522 at the
interface to the backplane. The hot insertion logic on the PCA9522 protects against
corrupted or truncated data transmissions on start-up of buffer operations.
Fig 7. PCA9522 typical buffer application
BUS MASTER
400 kHz
U1
V
CC
SCL
SDA
R1
600 Ω
R7
18 kΩ
SCLC
SDAC
1.8 V
EN
U2
PCA9522
V
CC
3.3 V
C1
0.01 μF
SCLB
SDAB
R3
3.9 kΩ
R4
3.9 kΩ
10 V
10 V
backplane
or cable run
SCLB
SDAB
EN
U3
PCA9522
V
CC
5 V
C2
0.01 μF
SCLC
SDAC
R5
1.1 kΩ
R6
1.1 kΩ
SCL
SDA
U4
V
CC
3.3 V
SLAVE
100 kHz
002aaf321
RDY
R2
600 Ω
RDY
