R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 15 of 16
Low Vcc Data Retention Characteristics
Parameter Symbol Min. Typ Max. Unit Test conditions
*3,4
V
CC
for data retention V
DR
2.0 - 3.6 V
Vin ≥ 0V
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ V
CC
-0.2V,
CS2 ≥ V
CC
-0.2V or
(3) LB# = UB# ≥ V
CC
-0.2V,
CS1# ≤ 0.2V,
CS2 ≥ V
CC
-0.2V
- 8
*1
24 μA ~+25°C
- 14
*2
48 μA ~+40°C
- - 100 μA ~+70°C
Data retention current I
CCDR
- - 160 μA ~+85°C
Vin ≥ 0V
BYTE# ≥ Vcc -0.2V or
BYTE# ≤0.2V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ V
CC
-0.2V,
CS2 ≥ V
CC
-0.2V or
(3) LB# = UB# ≥ V
CC
-0.2V,
CS1# ≤ 0.2V,
CS2 ≥ V
CC
-0.2V
Chip select to data retention
time
t
CDR
0 - - ns
Operation recovery time t
R
5 - - ms
See retention waveform.
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 40ºC), and not 100% tested.
3. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages.
4. CS2 also controls address buffer, WE# buffer ,CS1# buffer ,OE# buffer ,LB# ,UB# buffer and Din buffer. If
CS2 controls data retention mode, Vin levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high
impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or0V ≤ CS2 ≤ 0.2V.
The other input levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state.
