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9LPRS501SKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
IDT
TM
/ICS
TM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121G—05/19/11
Advance Information
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
19
Byte 0 FS Readback and PLL Selection Register
Bit Pin Name Description Type 0 1 Default
7
-
FSLC CPU Freq. Sel. Bit (Most Si
g
nificant)
R
Latch
6
-
FSLB CPU Freq. Sel. Bit
R
Latch
5
-
FSLA CPU Freq. Sel. Bit (Least Si
g
nificant)
R
Latch
4- iAMT_EN
Set via SMBus or dynamically by CK505 if
detects d
y
namic M1
RW Legacy Mode iAMT Enabled 0
3 Reserved Reserved RW 0
2 - SRC_Main_SEL Select source for SRC Main RW SRC Main = PLL1 SRC Main = PLL3 0
1 - SATA_SEL Select source for SATA clock RW SATA = SRC_Main
SATA = PLL2
See Note
0
0- PD_Restore
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold
power-on and go to latches open state
This bit is ignored and treated at '1' if device is in
iAMT mode.
RW Configuration Not Saved Configuration Saved 1
Note: If setting Byte 0, bit 1 to 1 to make SATA non-spreading, Byte63, bit 1 must be set to '1' first to turn on the SATA PLL.
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit Pin Name Description Type 0 1 Default
7 13/14 SRC0_SEL Select SRC0 or DOT96 RW SRC0 DOT96 0
6 - PLL1_SSC_SEL Select 0.5% down or center SSC RW Down spread Center spread 0
5 PLL3_SSC_SEL Select 0.5% down or center SSC RW Down spread Center spread 0
4 PLL3_CF3 PLL3 Quick Confi
g
Bit 3 RW 0
3 PLL3_CF2 PLL3 Quick Confi
g
Bit 2 RW 0
2 PLL3_CF1 PLL3 Quick Confi
g
Bit 1 RW 0
1 PLL3_CF0 PLL3 Quick Confi
g
Bit 0 RW 1
0 PCI_SEL PCI_SEL RW PCI from PLL1 PCI from SRC_MAIN 1
Byte 2 Output Enable Register
Bit Pin Name Description Type 0 1 Default
7 REF_OE Output enable for REF, if disabled output is Hi-Z RW Output Disabled Output Enabled 1
6 USB_OE Output enable for USB RW Output Disabled Output Enabled 1
5 PCIF5_OE Output enable for PCI5 RW Output Disabled Output Enabled 1
4 PCI4_OE Output enable for PCI4 RW Output Disabled Output Enabled 1
3 PCI3_OE Output enable for PCI3 RW Output Disabled Output Enabled 1
2 PCI2_OE Output enable for PCI2 RW Output Disabled Output Enabled 1
1 PCI1_OE Output enable for PCI1 RW Output Disabled Output Enabled 1
0 PCI0_OE Output enable for PCI0 RW Output Disabled Output Enabled 1
Byte 3 Output Enable Register
Bit Pin Name Description Type 0 1 Default
7 SRC11_OE Output enable for SRC11 RW Output Disabled Output Enabled 1
6 SRC10_OE Output enable for SRC10 RW Output Disabled Output Enabled 1
5 SRC9_OE Output enable for SRC9 RW Output Disabled Output Enabled 1
4 SRC8/ITP_OE Output enable for SRC8 or ITP RW Output Disabled Output Enabled 1
3 SRC7_OE Output enable for SRC7 RW Output Disabled Output Enabled 1
2 SRC6_OE Output enable for SRC6 RW Output Disabled Output Enabled 1
1 SRC5_OE Output enable for SRC5 RW Output Disabled Output Enabled 1
0 SRC4_OE Output enable for SRC4 RW Output Disabled Output Enabled 1
See Table 1 : CPU Frequency Select Table
See Table 2: PLL3 Quick Configuration
Only applies if Byte 0, bit 2 = 0.
Byte 4 Output Enable and Spread Spectrum Disable Register
Bit Pin Name Description Type 0 1 Default
7 SRC3_OE Out
p
ut enable for SRC3 R
W
Out
p
ut Disabled Out
p
ut Enabled 1
6 SATA/SRC2_OE Output enable for SATA/SRC2 RW Output Disabled Output Enabled 1
5 SRC1_OE Output enable for SRC1 RW Output Disabled Output Enabled 1
4 SRC0/DOT96_OE Output enable for SRC0/DOT96 RW Output Disabled Output Enabled 1
3 CPU1_OE Output enable for CPU1 RW Output Disabled Output Enabled 1
2 CPU0_OE Out
p
ut enable for CPU0 R
W
Out
p
ut Disabled Out
p
ut Enabled 1
1 PLL1_SSC_ON Enable PLL1's s
p
read modulation R
W
S
p
read Disabled S
p
read Enabled 1
0 PLL3_SSC_ON Enable PLL3's spread modulation RW Spread Disabled Spread Enabled 1
IDT
TM
/ICS
TM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121G—05/19/11
Advance Information
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
20
Byte 5 Clock Request Enable/Configuration Register
Bit Pin Name Description Type 0 1 Default
7 CR#_A_EN
Enable CR#_A (clk req),
PCI0_OE must be = 1 for this bit to take effect
RW Disable CR#_A Enable CR#_A 0
6 CR#_A_SEL Sets CR#_A to control either SRC0 or SRC2 RW CR#_A -> SRC0 CR#_A -> SRC2 0
5 CR#_B_EN Enable CR#_B
(
clk re
q)
RW Disable CR#_B Enable CR#_B 0
4 CR#_B_SEL Sets CR#_B -> SRC1 or SRC4 RW CR#_B -> SRC1 CR#_B -> SRC4 0
3 CR#_C_EN Enable CR#_C
(
clk re
q)
RW Disable CR#_C Enable CR#_C 0
2 CR#_C_SEL Sets CR#_C -> SRC0 or SRC2 RW CR#_C -> SRC0 CR#_C -> SRC2 0
1 CR#_D_EN Enable CR#_D (clk req) RW Disable CR#_D Enable CR#_D 0
0 CR#_D_SEL Sets CR#_D -> SRC1 or SRC4 RW CR#_D -> SRC1 CR#_D -> SRC4 0
Byte 6 Clock Request Enable/Configuration and Stop Control Register
Bit Pin Name Description Type 0 1 Default
7 CR#_E_EN Enable CR#_E
(
clk re
q)
-> SRC6 RW Disable CR#_E Enable CR#_E 0
6 CR#_F_EN Enable CR#_F (clk req) -> SRC8 RW Disable CR#_F Enable CR#_F 0
5 CR#_G_EN Enable CR#_G
(
clk re
q)
-> SRC9 RW Disable CR#_G Enable CR#_G 0
4 CR#_H_EN Enable CR#_H (clk req) -> SRC10 RW Disable CR#_H Enable CR#_H 0
3 Reserved Reserved RW 0
2 Reserved Reserved RW 0
1
SSCD_STP_CRTL
(
SRC1
)
If set, SSCD (SRC1) stops with PCI_STOP# RW Free Running
Stops with PCI_STOP#
assertion
0
0SRC_STP_CRTL
If set, SRCs (except SRC1) stop with
PCI_STOP#
RW Free Running
Stops with PCI_STOP#
assertion
0
Byte 7 Vendor ID/ Revision ID
Bit Pin Name Description Type 0 1 Default
7 Rev Code Bit 3 R X
6 Rev Code Bit 2 R X
5 Rev Code Bit 1 R X
4 Rev Code Bit 0 R X
3 Vendor ID bit 3 R 0
2 Vendor ID bit 2 R 0
1 Vendor ID bit 1 R 0
0 Vendor ID bit 0 R 1
Byte 8 Device ID and Output Enable Register
Bit Pin Name Description Type 0 1 Default
7
Device_ID3 R 0
6
Device_ID2 R 0
5
Device_ID1 R 0
4
Device_ID0 R 1
3 Reserved Reserved RW - - 0
2 Reserved Reserved RW - - 0
1 SE1_OE Out
p
ut enable for SE1 RW Disabled Enabled 0
0SE2_OE
Output enable for SE2
RW Disabled Enabled 0
Byte 9 Output Control Register
Bit Pin Name Description Type 0 1 Default
7 PCIF5 STOP EN
Allows control of PCIF5 with assertion of
PCI_STOP#
RW Free running
Stops with PCI_STOP#
assertion
0
6 TME_Readback Truested Mode Enable (TME) strap status
R
normal operation no overclocking 0
5 Reserved Reserved RW - - 1
4 Test Mode Select Allows test select, i
g
nores REF/FSC/TestSel RW Out
p
uts HI-Z Out
p
uts = REF/N 0
3 Test Mode Entry
Allows entry into test mode, ignores
FSB/TestMode
RW Normal operation Test mode 0
2 IO_VOUT2 IO Output Voltage Select (Most Significant Bit) RW 1
1 IO_VOUT1 IO Out
p
ut Volta
g
e Select RW 0
Revision ID
Vendor ID
ICS is 0001, binary
Table of Device identifier codes, used for
differentiating between CK505 package
options, etc.
Vendor specific
See Device ID Table
See Table 3: V_IO Selection
(Default is 0 8V)
IDT
TM
/ICS
TM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121G—05/19/11
Advance Information
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
21
Byte 10 CK505 Rev 0.85 Functions (ICS Rev H Silicon and Higher)
Bit Pin Name Description Type 0 1 Default
7 SRC5_EN Readback Readback of SRC5 enable latch
R
CPU/PCI Stop Enabled SRC5 Enabled Latch
6 Reserved RW TBD TBD 0
5 Reserved RW TBD TBD 0
4 Reserved RW TBD TBD 0
3 Reserved RW TBD TBD 0
2 Reserved RW TBD TBD 0
1 CPU 1 Stop Enable Enables control of CPU1 with CPU_STOP# RW Free Running Stoppable 1
0 CPU 0 Stop Enable Enables control of CPU 0 with CPU_STOP# RW Free Running Stoppable 1
Byte 11 CK505 Rev 1.0 functions (ICS Rev P silicon and higher)
Bit Pin Name Description Type 0 1 Default
7 Reserved RW TBD TBD 0
6 Reserved RW TBD TBD 0
5 Reserved RW TBD TBD 0
4 Reserved RW TBD TBD 0
3 CPU2_iAMT_EN Enables CPU2(ITP) output in iAMT state (M1) RW Off in iAMT Free running in iAMT 0
2 CPU1_iAMT_EN Enables CPU1 output in iAMT state (M1) RW Off in iAMT Free runnin
g
in iAMT 1
1 PCIe-Gen2 PCIe-Gen2 status
R
PCIe Gen1 compliant PCIe Gen2 compliant 0
0 CPU2 Stop Enable Enables control of CPU2(ITP) with CPU_STOP# RW Free Running Stoppable 1
Byte 12 Byte Count Register
Bit Pin Name Description Type 0 1 Default
7 Reserved RW 0
6 Reserved RW 0
5 BC5 RW 0
4 BC4 RW 0
3 BC3 RW 1
2 BC2 RW 1
1 BC1 RW 0
0 BC0 RW 1
Byte 13 CK505 PLL1 M/N Programming Register
Bit Pin Name Description Type 0 1 Default
7
N Div8 N Divider 8 RW - - X
6
N Div9 N Divider 9 RW - - X
5
M Div5 RW - - X
4
M Div4 RW - - X
3
M Div3 RW - - X
2
M Div2 RW - - X
1
M Div1 RW - - X
0
M Div0 RW - - X
Byte 14 CK505 PLL1 M/N Programming Register
Bit Pin Name Description Type 0 1 Default
7
N Div7 RW - - X
6
N Div6 RW - - X
5
N Div5 RW - - X
4
N Div4 RW - - X
3
N Div3 RW - - X
2
N Div2 RW - - X
1
N Div1 RW - - X
0
N Div0 RW - - X
The decimal representation of M Div (5:0) is equal
to reference divider value. Default at power up =
latch-in or Byte 0 Rom table.
Read Back byte count register
The decimal representation of N Div (9:0) is equal
to VCO divider value. Default at power up = latch
-
in or Byte 0 Rom table.
Reserved
Reserved
Byte 15 CK505 PLL1 Spread Spectrum Control Register
Bit Pin Name Description Type 0 1 Default
7
SSP7 RW - - X
6
SSP6 RW - - X
5
SSP5 RW - - X
4
SSP4 RW - - X
3
SSP3 RW - - X
2
SSP2 RW - - X
1
SSP1 RW - - X
0
SSP0 RW - - X
These Spread Spectrum bits will program the
spread pecentage. Contact ICS for the correct
values.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

9LPRS501SKLF

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Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
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