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9LPRS501SKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
IDT
TM
/ICS
TM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121G—05/19/11
Advance Information
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
25
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa C
MIN MAX MIN MAX
A--1.20--.047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
α
0° 8° 0° 8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
64 16.90 17.10 .665 .673
10-0039
6.10 mm. Bod
y
, 0.50 mm. Pitch TSSOP
(
240 mil
)
(
20 mil
)
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS SEE VARIATIONS
8.10 BASIC 0.319 BASIC
0.50 BASIC 0.020 BASIC
SEE VARIATIONS SEE VARIATIONS
N
D mm. D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
IDT
TM
/ICS
TM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121G—05/19/11
Advance Information
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
26
E
Top View
OR
Anvil
Singulation
A3
L
N
(Ref.)
e
e
e
e
(Ref. )
(Ref. )
(Ref. )
(Typ.)
If
A1
Even
E2
D2
D2
2
A
C
0.08
C
E2
2
2
2
1
Sawn
Singulation
Index Area
Seating Plane
are Even
Thermal
Base
Odd
b
(N - 1)x
N
1
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D
D
&
&N
D
N
D
N
E
N
E
&N
D
N
E
(N - 1)x
E
DIMENSIONS OPTION 1 DIMENSIONS (mm) OPTION 2 DIMENSIONS (mm)
SYMBOL MIN. MAX. SYMBOL MIN. MAX.
A 0.8 1.0 A 0.8 1.0
N 64 A1 0 0.05 A1 0 0.05
N
D
16 A3 A3
N
E
16 b 0.18 0.3 b 0.18 0.3
ee
D x E BASIC D x E BASIC
D2 MIN. / MAX. 7. 00 7.25 D2 MIN. / MAX. 6.00 6.25
E2 MIN. / MAX. 7.00 7.25 E2 MIN. / MAX. 6.00 6.25
L MIN. / MAX. 0.30 0.50 L MIN. / MAX. 0.30 0.50
0.25 Reference
0.50 BASIC
9.00 x 9.00
0.25 Ref erence
0.50 BASIC
9.00 x 9.00
THERMALLY ENHANCED, VE RY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
SYMBOL 64L
Ordering Information
Part / Order Number Shipping Packaging Package Temperature
9LPRS501SGLF Tubes 64-pin TSSOP 0 to +70° C
9LPRS501SGLFT Tape and Reel 64-pin TSSOP 0 to +70° C
9LPRS501SKLF Trays 64-pin MLF 0 to +70° C
9LPRS501SKLFT Tape and Reel 64-pin MLF 0 to +70° C
“LF” suffix to the part number are the Pb-Free configuration, RoHS compliant.
27
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-6578
pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks
or registered trademarks used to identify products or services of their respective owners.
Printed in USA
TM
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
This product is protected by United States Patent NO. 7,342,420 and other patents.
Rev. Issue Date Description Page #
A 2/15/2008
1. Updated PLL3 Configuration Table.
2. Release to Final. -
B 4/25/2008 Updated note on B
y
te 63. 24
C 9/3/2008
1. Updated Electrical Table.
2. Udpated SMBus Byte 9.
12,
21
D 9/30/2008 Added case temperature 12
E 11/12/2008 Added Electrical table for SE1/2=25MHz. 15
F 2/23/2009 Updated note under Byte 63 table. 24
G 5/19/2011
1. Updated Electrical Tables to latest CK505 format
2. Added note to SMBus byte 0 clarifying interaction with Byte 63
3. Updated ordering information to latest format
12-15, 20,
22, 26, 27
Revision History
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

9LPRS501SKLF

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Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
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