NCV3843BV
http://onsemi.com
10
Undervoltage Lockout
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (V
CC
) and the reference output (V
ref
) are
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The V
CC
comparator
upper and lower thresholds are 8.4 V/7.6 V for the
NCV3843BV. The V
ref
comparator upper and lower
thresholds are 3.6 V/3.4 V. The NCV3843BV is intended for
lower voltage DC−to−DC converter applications. A 36 V
Zener is connected as a shunt regulator from V
CC
to ground.
Its purpose is to protect the IC from excessive voltage that
can occur during system startup. The minimum operating
voltage (V
CC
) for the NCV3843BV is 8.2 V.
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull−down resistor.
The SOIC−14 surface mount package provides separate
pins for V
C
(output supply) and Power Ground. Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the I
pk(max)
clamp level. The separate V
C
supply input allows the
designer added flexibility in tailoring the drive voltage
independent of V
CC
. A Zener clamp is typically connected
to this input when driving power MOSFETs in systems
where V
CC
is greater than 20 V. Figure 26 shows proper
power and control ground connections in a current−sensing
power MOSFET application.
Reference
The 5.0 V bandgap reference is trimmed to ±2.0% on the
NCV3843BV. Its primary purpose is to supply charging
current to the oscillator timing capacitor. The reference has
short− circuit protection and is capable of providing in
excess of 20 mA for powering additional control system
circuitry.
Design Considerations
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse−width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 mF) connected directly to V
CC
, V
C
,
and V
ref
may be required depending upon circuit layout.
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise−generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulator’s closed loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 20A
shows the phenomenon graphically. At t
0
, switch
conduction begins, causing the inductor current to rise at a
slope of m
1
. This slope is a function of the input voltage
divided by the inductance. At t
1
, the Current Sense Input
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
a slope of m
2
, until the next oscillator cycle. The unstable
condition can be shown if a perturbation is added to the
control voltage, resulting in a small DI (dashed line). With
a fixed oscillator period, the current decay time is reduced,
and the minimum current at switch turn−on (t
2
) is increased
by DI + DI m
2
/m
1
. The minimum current at the next cycle
(t
3
) decreases to (DI + DI m
2
/m
1
) (m
2
/m
1
). This perturbation
is multiplied by m
2
/m
1
on each succeeding cycle, alternately
increasing and decreasing the inductor current at switch
turn−on. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
commence again. If m
2
/m
1
is greater than 1, the converter
will be unstable. Figure 20B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the DI perturbation will decrease to zero
on succeeding cycles. This compensating ramp (m
3
) must
have a slope equal to or slightly greater than m
2
/2 for
stability. With m
2
/2 slope compensation, the average
inductor current follows the control voltage, yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 33).
