71024S15TYGI

6.42
4
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
71024S12 71024S15 71024S20
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
Read Cycle
t
RC
Read Cycle Time 12 15 20 ns
t
AA
Address Access Time 12 15 20 ns
t
ACS
Chip Select Access Time 12 15 20 ns
t
CL Z
(1 )
Chip Select to Output in Low-Z 3 3 3 ns
t
CHZ
(1)
Chip Deselect to Output in High-Z 0 6 0 7 0 8 ns
t
OE
Output Enable to Output Valid 6 7 8 ns
t
OLZ
(1 )
Output Enab le to Output in Low-Z 0 0 0 ns
t
OHZ
(1 )
Output Disable to Output in High-Z 0 5 0 5 0 7 ns
t
OH
Output Hold from Address Change 4 4 4 ns
t
PU
(1)
Chip Select to Power-Up Time 0—0—0—ns
t
PD
(1)
Chip Deselect to Power-Down Time 12 15 20 ns
Write Cycle
t
WC
Write Cycle Time 12 15 20 ns
t
AW
Address Valid to End-of-Write 10 12 15 ns
t
CW
Chip Select to End-of-Write 10 12 15 ns
t
AS
Address Set-Up Time 0—0—0—ns
t
WP
Write Pulse Width 8 12 15 ns
t
WR
Write Recovery Time 0—0—0—ns
t
DW Data Valid to End-of-Write 7—8—9—ns
t
DH
Data Hold Time 0—0—0—ns
t
OW
(1)
Output Active from End-of-Write 3 3 4 ns
t
WHZ
(1)
Write Enable to Output in High-Z 0 5 0 5 0 8 ns
2964 tbl 09
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
6.42
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
5
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Read Cycle No. 1
(1)
Timing Waveform of Read Cycle No. 2
(1,2,4)
6.42
6
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1
(WE Controlled Timing)
(1,4,6)
Timing Waveform of Write Cycle No. 2
(CS
1 AND CS2 Controlled Timing)
(1,4)
NOTES:
1. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE.
2. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS1 LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS1 and CS2 must
both be active during the tCW write period.
5. Transition is measured ±200mV from steady state.
6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.

71024S15TYGI

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 128Kx8 ASYNCHRONOUS 5.0V STATIC RAM
Lifecycle:
New from this manufacturer.
Delivery:
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