LTC692/LTC693
10
0692fb
The LTC692/LTC693 are protected for safe area operation
with a short-circuit limit. Output current is limited to ap-
proximately 200mA. If the device is overloaded for long
periods of time, thermal shutdown turns the power switch
off until the device cools down. The threshold temperature
for thermal shutdown is approximately 155°C with about
10°C of hysteresis which prevents the device from oscil-
lating in and out of shutdown.
The PNP switch used in competitive devices was not chosen
for the internal power switch because it injects unwanted
current into the substrate. This current is collected by the
V
BATT
pin in competitive devices and adds to the charging
current of the battery which can damage lithium batteries.
The LTC692/LTC693 use a charge-pumped NMOS power
switch to eliminate unwanted charging current while
achieving low dropout and low supply current. Since no
current goes to the substrate, the current collected by the
V
BATT
pin is strictly junction leakage.
A 125Ω PMOS switch connects the V
BATT
input to V
OUT
in
battery backup mode. The switch is designed for very low
dropout voltage (input-to-output differential). This feature
is advantageous for low current applications such as bat-
tery backup in CMOS RAM and other low power CMOS
circuitry. The supply current in battery backup mode is
1μA maximum.
The operating voltage at the V
BATT
pin ranges from 2.0V to
4.0V. High value capacitors, such as electrolytic or farad-
size double layer capacitors, can be used for short-term
memory backup instead of a battery. The charging resistor
for the rechargeable batteries should be connected to V
OUT
since this eliminates the discharge path that exists when
the resistor is connected to V
CC
(Figure 3).
Replacing the Backup Battery
When changing the backup battery with system power on,
spurious resets can occur while the battery is removed
due to battery standby current. Although battery standby
current is only a tiny leakage current, it can still charge up
the stray capacitance on the V
BATT
pin. The oscillation cycle
is as follows: When V
BATT
reaches within 50mV of V
CC
,
the LTC692/LTC693 switch to battery backup. V
OUT
pulls
V
BATT
low and the devices go back to normal operation.
The leakage current then charges up the V
BATT
pin again
and the cycle repeats.
If spurious resets during battery replacement pose no
problems, then no action is required. Otherwise, a resistor
from V
BATT
to GND will hold the pin low while changing
the battery. For example, the battery standby current is
1μA maximum over temperature and the external resistor
required to hold V
BATT
below V
CC
is:
R
V 50mV
1A
CC
μ
With V
CC
= 4.25V, a 3.9M resistor will work. With a 3V
battery, this resistor will draw only 0.77μA from the bat-
tery, which is negligible in most cases.
APPLICATIONS INFORMATION
5V
3V
0.1μF
0.1μF
V
BATT
V
CC
LTC693
V
OUT
GND
4
3
1
2
5
ANY PNP POWER TRANSISTOR
692_3 • F02
BATT ON
5V
3V
0.1μF
0.1μF
692_3 • F03
V
OUT
– V
BATT
R
I =
R
V
BATT
V
CC
LTC692
LTC693
V
OUT
GND
Figure 2. Using BATT ON to Drive External PNP Transistor Figure 3. Charging External Battery Through V
OUT
LTC692/LTC693
11
0692fb
If battery connections are made through long wires, a
10Ω to 100Ω series resistor and a 0.1μF capacitor are
recommended to prevent any overshoot beyond V
CC
due
to the lead inductance (Figure 4).
Table 1 shows the state of each pin during battery backup.
When the battery switchover section is not used, connect
V
BATT
to GND and V
OUT
to V
CC
.
battery backed up CMOS RAM. CE OUT can also be used
to drive the Store or Write input of an EEPROM, EAROM
or NOVRAM to achieve similar protection. Figure 5 shows
the timing diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessors address
decoder output. Figure 6 shows a typical nonvolatile CMOS
RAM application.
Memory protection can also be achieved with the LTC692
by using RESET as shown in Figure 7.
APPLICATIONS INFORMATION
3.9M
0.1μF
V
BATT
LTC692
LTC693
GND
692_3 • F04
10Ω
Figure 4. 10Ω/0.1μF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement
Table 1. Input and Output Status in Battery Backup Mode
SIGNAL STATUS
V
CC
C2 monitors V
CC
for active switchover
V
OUT
V
OUT
is connected to V
BATT
through an internal PMOS switch
V
BATT
The supply current is 1μA maximum
BATT ON Logic high. The open-circuit output voltage is equal to V
OUT
PFI Power failure input is ignored
PFO Logic low
RESET Logic low
RESET Logic high. The open-circuit output voltage is equal to V
OUT
LOW LINE Logic low
WDI Watchdog input is ignored
WDO Logic high. The open-circuit output voltage is equal to V
OUT
CE IN Chip Enable input is ignored
CE OUT Logic high. The open-circuit output voltage is equal to V
OUT
OSC IN OSC IN is ignored
OSC SEL OSC SEL is ignored
Memory Protection
The LTC693 includes memory protection circuitry which
ensures the integrity of the data in memory by preventing
write operations when V
CC
is at an invalid level. Two ad-
ditional pins, CE IN and CE OUT, control the Chip Enable
or Write inputs of CMOS RAM. When V
CC
is 5V, CE OUT
follows CE IN with a typical propagation delay of 20ns.
When V
CC
falls below the reset voltage threshold or V
BATT
,
CE OUT is forced high, independent of CE IN. CE OUT is
an alternative signal to drive the CE, CS, or Write input of
V
CC
V1
CE IN
V
OUT
= V
BATT
CE OUT
V
OUT
= V
BATT
V2
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
692_3 • F05
Figure 5. Timing Diagram for CE IN and CE OUT
LTC692/LTC693
12
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Power-Fail Warning
The LTC692/LTC693 generate a power failure output
(PFO) for early warning of failure in the microprocessors
power supply. This is accomplished by comparing the
power failure input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 5V output. The volt-
age divider ratio can be chosen such that the voltage at
the PFI pin falls below 1.3V, several milliseconds before
the 5V supply falls below the maximum reset voltage
threshold of 4.50V. PFO is normally used to interrupt the
microprocessor to execute shutdown procedure between
PFO and RESET or RESET.
APPLICATIONS INFORMATION
5V
3V
0.1μF
10μF
V
BATT
V
CC
LTC693
V
OUT
GND
692_3 • F06
V
CC
RESET
CE IN
CE OUT
RESET
0.1μF
TO μP
FROM DECODER
CS
20ns PROPAGATION DELAY
62512
RAM
GND
+
5V
3V
0.1μF
10μF
V
BATT
V
CC
LTC692
V
OUT
GND
692_3 • F07
V
CC
RESET
0.1μF
CS
62128
RAM
CS1
CS2
GND
+
Figure 6. A Typical Nonvolatile CMOS RAM Application
Figure 7. Write-Protect for RAM with the LTC692
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resistor
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the sum-
ming junction at the PFI pin.
V =1.3V 1+
R1
R2
R1
R3
H
+
When PFO output is high, the series combination of R3
and R4 source current into the PFI summing junction.
V 1.3V 1
R1
R2
(5V 1.3V)R1
1.3V(R3 R4)
L
=+
+
A
sssumingR4 R3,V 5V
R1
R3
HYSTERESIS
<< =

LTC692IS8#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits uP Supervisor with Watchdog
Lifecycle:
New from this manufacturer.
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