LTC692/LTC693
7
0692fb
PIN FUNCTIONS
BATT ON: Battery On Logic Output from Comparator C2.
BATT ON goes low when V
OUT
is internally connected to
V
CC
. The output typically sinks 35mA and can provide base
drive for an external PNP transistor to increase the output
current above the 50mA rating of V
OUT
. BATT ON goes high
when V
OUT
is internally switched to V
BATT
.
CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See Applications Information section and
Figure 5 for additional information.
CE OUT : Logic Output on the Chip Enable Gating Circuit.
When V
CC
is above the reset voltage threshold, CE OUT is
a buffered replica of CE IN. When V
CC
is below the reset
voltage threshold CE OUT is forced high (see Figure 5).
GND: Ground Pin.
LOW LINE: Logic Output from Comparator C1. LOW LINE
indicates a low line condition at the V
CC
input. When V
CC
falls below the reset voltage threshold (4.40V typically),
LOW LINE goes low. As soon as V
CC
rises above the reset
voltage threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when V
CC
drops below V
BATT
(see
Table 1).
OSC IN: Oscillator Input. OSC IN can be driven by an
external clock signal or an external capacitor can be
connected between OSC IN and GND when OSC SEL is
forced low. In this confi guration the nominal reset active
time and watchdog timeout period are determined by the
number of clocks or set by the formula (see Applications
Information section). When OSC SEL is high or fl oating,
the internal oscillator is enabled and the reset active time
is fi xed at 200ms typical. OSC IN selects between the 1.6
seconds and 100ms typical watchdog timeout periods. In
both cases the timeout period immediately after a reset is
1.6 seconds typical.
OSC SEL: Oscillator Selection Input. When OSC SEL is
high or fl oating, the internal oscillator sets the reset active
time and watchdog timeout period. Forcing OSC SEL low
allows OSC IN to be driven from an external clock signal
or an external capacitor to be connected between OSC
IN and GND.
PFI: Power Failure Input. PFI is the noninverting input
to the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes
low when PFI is below 1.3V. Connect PFI to GND or V
OUT
when C3 is not used.
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When V
CC
is lower than V
BATT
, C3 is shut down and
PFO is forced low.
RESET: Logic Output for μP Reset Control. Whenever V
CC
falls below either the reset voltage threshold (4.40V typi-
cally) or V
BATT
, RESET goes active low. After V
CC
returns
to 5V, reset pulse generator forces RESET to remain active
low for a minimum of 140ms. When the watchdog timer is
enabled but not serviced prior to a preset timeout period,
reset pulse generator also forces RESET to active low for
a minimum of 140ms for every preset timeout period
(see Figure 11). The reset active time is adjustable on
the LTC693. An external pushbutton reset can be used in
connection with the RESET output. See Pushbutton Reset
in the Applications Information section.
RESET: RESET is an Active High Logic Output. It is the
inverse of RESET.
V
BATT
: Backup Battery Input. When V
CC
falls below V
BATT
,
auxiliary power connected to V
BATT
is delivered to V
OUT
through PMOS switch, M2. If backup battery or auxiliary
power is not used, V
BATT
should be connected to GND.
V
CC
: 5V Supply Input. The V
CC
pin should be bypassed
with a 0.1μF capacitor.
V
OUT
: Voltage Output for Backed-Up Memory. Bypass with
a capacitor of 0.1μF or greater. During normal operation,
V
OUT
obtains power from V
CC
through an NMOS power
switch, M1, which can deliver up to 50mA and has a typical
on-resistance of 5Ω. When V
CC
is lower than V
BATT
, V
OUT
is internally switched to V
BATT
. If V
OUT
and V
BATT
are not
used, connect V
OUT
to V
CC
.
