LT6555
10
6555f
To maintain the LT6555’s channel isolation, it is beneficial
to shield parallel input and parallel output traces using a
ground plane or power supply traces. Vias between topside
and backside metal may be required to maintain a low
inductance ground near the part where numerous traces
converge. See Figures 6 and 7 for photos of an optimized
layout.
Input Expansion
In applications with more than two inputs per channel,
multiple LT6555s can be connected by several different
methods. The simplest method is to connect the outputs
after the 75 series termination, as shown in Figure 2. The
compromise of this approach is that the internal gain
setting resistors cause a 435 shunt across the 75 cable
termination, resulting in increased gain error.
APPLICATIO S I FOR ATIO
WUUU
Figure 3. Disabled Amplifiers Load the Cable
Termination with 435 Each
Figure 3 illustrates the loading effect of expanding the
number of inputs. The resultant gain error can be calcu-
lated by the following formula using n as the number of
LT6555s:
For example, two LT6555s would result in a gain error of
–0.74dB per channel. Three LT6555s (i.e., six red inputs,
six green inputs and six blue inputs), would have a gain
error of –1.4dB.
Figure 2. Two LT6555s Build a 4-Input Router
IN1A
IN1B
IN1C
IN1D
CHIP
SELECT
6555 F02
EN
LT6555 #1
75
A
V
= 2
LT6555 #2
74HC04
EN
75
OUT
A
V
= +2
75
CABLE
75
R2
75
6555 F03
360
IN1A
IN1C
IN1B
IN1D
75
1/3 LT6555 #1
1/3 LT6555 #2
360
OFF
360
360
OFF
360
75
75
360
OFF
360
360
ON
435
n – 1
n = NUMBER OF LT6555s
IN PARALLEL
.
.
.
n
LT6555
11
6555f
APPLICATIO S I FOR ATIO
WUUU
This systematic gain error can be significantly reduced by
lowering the value of the 75 series termination resistors.
The compromise of this approach is an increased depen-
dence on the accuracy of the 75 shunt termination at the
receiving end of the line. A table of values for 1% series
termination resistors from n = 2 to n = 4 is shown below.
NUMBER OF DEVICES (n) SERIES R
T
2 63.9
3 56.2
4 49.9
Another approach that does not compromise gain accu-
racy is to connect the outputs directly together before the
series termination. In this case, there will be slightly
increased output glitching and supply current spiking
during the EN pin switching, but the additional output
loading will not increase the gain error, and the series
termination resistors remain at their ideal value for AC
response. See Figure 4 for a scope photo showing the
result of the outputs connected both before and after the
series terminations, and Figure 8 for a full schematic of a
4:1 RGB multiplexer with the output pins directly con-
nected together. It is imperative that the output traces be
as short as possible before the series termination in order
to reduce capacitance and minimize AC peaking.
Figure 4. 4-Input Router Switching with Outputs Directly
Connected and with Outputs Connected After 63.9
Series Termination
ESD Protection
The LT6555 has reverse-biased ESD protection diodes on
all pins. If any pins are forced a diode drop above the
positive supply or a diode drop below the negative supply,
large currents may flow through these diodes. If the
current is kept below 10mA, no damage to the devices will
occur.
TIME (µs)
0
MULTIPLEXED OUTPUT (V)
SUPPLY CURRENT (mA)
–0.5
0
0.5
4
6555 F04
–1.0
1
2
3
0.5
1.5
2.5
3.5
1.5
1.0
0
50
I
S
I
S
+
100
150
V
S
= ±5V
V
IN(AMP1)
= –0.5V
V
IN(AMP2)
= 0.5V
R
L
= 150
OUTPUTS
DIRECTLY
CONNECTED
SERIES 63.9
AT EACH OUTPUT
TYPICAL APPLICATIO
U
RGB Multiplexer Demo Board
The DC858A Demo Board illustrates optimal routing,
bypassing and termination using the LT6555 as an
RGB video multiplexer. The schematic is shown in Fig-
ure 5. All inputs and outputs are routed to have a charac-
teristic impedance of 75 and 75 input shunt and output
series terminations are connected as close to the part as
possible. The board is fabricated with four layers with
internal ground and power planes. For ideal operation, a
75 load termination should be connected at the output.
The LT6555’s gain of 2 will compensate for the resulting
divider between the series and load termination resistors.
Figures 6 and 7 show the topside and bottom side board
layout and placement.
LT6555
12
6555f
Figure 5. Demo Board Schematic
5
IN1A
4
3
2
5
IN2A
4
3
2
5
IN3A
4
3
2
5
IN1B
4
3
2
5
IN2B
4
3
2
5
IN3B
4
3
2
IN1B
AGND1
IN3A
V
REF
V
REF
IN2A
DGND
DGND
IN1A
AGND2
8
9
10
11
12
7
6
5
4
3
2
1
17
16
15
14
13
18
19
20
21
22
23
24
V
+
OUT2
V
OUT1
IN3B
AGND3
IN2B
V
V
+
V
+
V
OUT3
V
+
SEL
SEL
EN
V
+
U1 LT6555CGN
EXT GND
13
2
JP5
V
REF
JP12
BNC × 6
DGND
1
1
1
1
1
1
L1
L1
L1
L1
L1
L1
Z = 75
Z = 75
Z = 75
Z = 75
Z = 75
Z = 75
JP13
JP14
JP5
JP6
JP7
J3
BANANA JACK
FLOAT AGND
13
2
JP2
DGND
EXT ENABLE
13
2
JP1
CONTROL
13
V
CC
SEL A/B
AB
DGND
2
JP4
SEL
R7
20k
J1
50 BNC
EN
5432
1
R10
75
R11
75
R12
75
R4
75
R5
75
R6
75
2
DUAL
NOTE:
470pF BYPASS CAPACITORS LOCATED
AS CLOSE TO PINS AS POSSIBLE
SINGLE
AGND
JP3
SUPPLY
31
E1
EN
E4
SEL A/B
E2
DGND
E5
V
REF
E3
AGND
R8
50
OPT
Z = 50 Z = 50
EN
5
OUT1
J9
1L2
L2
L2
Z = 75
R1
75
R2
75
R3
75
Z = 75
Z = 75
1
1
J10
J11
J4
BANANA JACK
V
EE
6555 F05
4
3
2
5
OUT2
4
3
2
5
OUT3
V
EE
–3.3V TO –5V
4
3
2
C1
4700pF
C10
4700pF
C11
0.33µF
16V
C2
470pF
C3
470pF
C4
10µF
16V
1206
C7
470pF
J2
BANANA JACK
V
CC
V
CC
3.3V TO 5V
C8
0.33µF
C5
4700pF
C6
470pF
C9
10µF
16V
1206
BNC × 3
5432
1
R9
50
OPT
J8
50 BNC
Figure 6. Demo Board Topside
(IC Removed for Clarity)
Figure 7. Demo Board Bottom Side
TYPICAL APPLICATIO
U

LT6555IGN#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video Switch ICs 650MHz Gain of 2 3x 2:1Video Multxer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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