LT6555IGN#PBF Datasheet LT6555CUF#PBF, LT6555IGN#PBF, LT6555CGN#PBF | P7-P9

LT6555

6555f

IN1A (Pin 1): Channel 1 Input A. This pin has a nominal

impedance of 400kΩ and does not have any internal

termination resistor.

DGND (Pin 2): Digital Ground Reference for Enable Pin.

This pin is normally connected to ground.

IN2A (Pin 3): Channel 2 Input A. This pin has a nominal

impedance of 400kΩ and does not have any internal

termination resistor.

REF

(Pin 4): Voltage Reference for Input Clamping. This

is the tap to an internal voltage divider that defines mid-

supply. It is normally connected to ground in dual supply,

DC coupled applications.

IN3A (Pin 5): Channel 3 Input A. This pin has a nominal

impedance of 400kΩ and does not have any internal

termination resistor.

AGND1 (Pin 6): Analog Ground for the 360Ω Gain Resis-

tor of Channel 1.

IN1B (Pin 7): Channel 1 Input B. This pin has a nominal

impedance of 400kΩ and does not have any internal

termination resistor.

AGND2 (Pin 8): Analog Ground for the 360Ω Gain Resis-

tor of Channel 2.

IN2B (Pin 9): Channel 2 Input B. This pin has a nominal

impedance of 400kΩ and does not have any internal

termination resistor.

AGND3 (Pin 10): Analog Ground for the 360Ω Gain

Resistor of Channel 3.

IN3B (Pin 11): Channel 3 Input B. This pin has a nominal

impedance of 400kΩ and does not have any internal

termination resistor.

–

(Pin 12): Negative Supply Voltage. V

–

pins are not in-

ternally connected to each other and must all be connected

externally. Proper supply bypassing is necessary for best

performance. See the Applications Information section.

(Pins 13, 14, 24): Positive Supply Voltage. V

pins are

not internally connected to each other and must all be

connected externally. Proper supply bypassing is neces-

sary for best performance. See the Applications Informa-

tion section.

–

(Pin 15): Negative Supply Voltage for Channel 3 Output

Stage. V

–

pins are not internally connected to each other

and must all be connected externally. Proper supply bypass-

ing is necessary for best performance. See the Applications

Information section.

OUT3 (Pin 16): Channel 3 Output. It is twice the selected

channel 3 input and performs optimally with a 150Ω load

(a double terminated 75Ω cable).

(Pin 17): Positive Supply Voltage for Channels 2 and 3

Output Stages. V

pins are not internally connected to each

other and must all be connected externally. Proper supply

bypassing is necessary for best performance. See the

Applications Information section.

OUT2 (Pin 18): Channel 2 Output. It is twice the selected

channel 2 input and performs optimally with a 150Ω load

(a double terminated 75Ω cable).

–

(Pin 19): Negative Supply Voltage for Channels 1 and

2 Output Stages. V

–

pins are not internally connected to each

other and must all be connected externally. Proper supply

bypassing is necessary for best performance. See the Ap-

plications Information section.

OUT1 (Pin 20): Channel 1 Output. It is twice the selected

channel 1 input and performs optimally with a 150Ω load

(a double terminated 75Ω cable).

(Pin 21): Positive Supply Voltage for Channel 1 Output

Stage. V

pins are not internally connected to each other

and must all be connected externally. Proper supply

bypassing is necessary for best performance. See the

Applications Information section.

SEL (Pin 22): Select Pin. This high impedance pin selects

which set of inputs are sent to the output pins. When the

pin is pulled low, the A inputs are selected. When the pin

is pulled high, the B inputs are selected.

EN (Pin 23): Enable Control Pin. An internal pull-up

resistor of 46k defines the pin’s impedance and will turn

the part off if the pin is unconnected. When the pin is pulled

low, the amplifiers are enabled.

Exposed Pad (Pin 25, QFN Only): The Exposed Pad is V

–

and must be soldered to the PCB. It is internally connected

to the QFN Pin 4, V

–

PI FU CTIO S

(GN24 Package)

LT6555

6555f

Power Supplies

The LT6555 is optimized for ±5V supplies but can be

operated on as little as ±2.25V or a single 4.5V supply and

as much as ±6V or a single 12V supply. Internally, each

supply is independent to improve channel isolation. Do

not leave any supply pins disconnected or the part may

not function correctly!

Enable/Shutdown

The LT6555 has a shutdown mode controlled by the EN

pin and referenced to the DGND pin. If the amplifier will

be enabled at all times, the EN pin can be connected

directly to DGND. If the enable function is desired, either

driving the pin above 2V or allowing the internal 46k pull-

up resistor to pull the EN pin to the top rail will disable the

amplifier. When disabled, the DC output impedance will

rise to approximately 360Ω through the internal feedback

and gain resistors. Supply current into the amplifier in the

disabled state will be:

–

46 80

It is important that the following constraints on the DGND,

EN and SEL pins are always followed:

– V

DGND

≥ 4.5V

– V

DGND

≤ 5.5V

SEL

– V

DGND

≤ 8V

In dual supply cases where V

is less than 4.5V, DGND

should be connected to a potential below ground, such as

–

. Since the EN and SEL pins are referenced to DGND,

they may need to be pulled below ground in those cases.

In single supply applications above 5.5V, an additional

resistor may be needed from the EN pin to DGND if the pin

is ever allowed to float. For example, on a 12V single

supply, a 33k resistor would protect the pin from floating

too high while still allowing the internal pull-up resistor to

disable the part.

On dual ±2.25V supplies, connecting the DGND pin to V

–

is the only way of ensuring that V

– V

DGND

≥ 4.5V.

The DGND pin should not be pulled above the EN pin since

doing so will turn on an ESD protection diode. If the EN pin

voltage is forced a diode drop below the DGND pin, current

should be limited to 10mA or less.

The enable/disable times of the LT6555 are fast when

driven with a logic input. Turn on (from 50% EN input to

50% output) typically occurs in less than 50ns. Turn off is

slower, but is typically below 500ns.

Channel Select

The SEL pin uses the same internal threshold as the EN pin

and is also referenced to DGND. When the pin is logic low,

the channel A inputs are passed to the output. When the

pin is logic high, the channel B inputs are passed to the

output. The pin should not be floated but can be tied to

DGND to force the outputs to always be channel A or to V

(when less than 8V) to force the outputs to always be

channel B.

Truth Table

SEL A/B EN OUT

002 × IN A

102 × IN B

X 1 OFF

Input Considerations

The LT6555 uses input clamps referenced to the V

REF

to prevent damage to the input stage on the unselected

channel. Three transistors in series limit the input voltage

to within three diode drops (±) from V

REF

. V

REF

is nomi-

nally set to half of the sum of the supplies by the 40k

resistors. A simplified schematic is shown in Figure 1.

To improve clamping, the pin’s DC impedance should be

minimized by connecting the V

REF

pin directly to ground in

the symmetric dual supply case with a common mode

voltage of 0V. While loaded output swing limits the useful

input voltage range in that case, if the common mode

voltage is not centered at ground or the input voltage

exceeds plus or minus three diodes from ground, an

external resistor to either supply can be added to shift the

APPLICATIO S I FOR ATIO

WUU

LT6555

6555f

APPLICATIO S I FOR ATIO

WUUU

REF

voltage to the desired level. The only way to cover the

full common mode voltage range of V

–

+ 1V to V

– 1V is

to shift V

REF

up or down. Note that on a single supply, the

unclamped input range limits the output low swing to 2V

(1V multiplied by the internal gain of 2).

The V

REF

pin can also be directly driven with a DC source.

Bypassing the V

REF

pin is not necessary.

The inputs can be driven beyond the point at which the

output clips so long as input currents are limited to less

than ±10mA. Continuing to drive the input beyond the

output limit can result in increased current drive and

slightly increased swing, but will also increase supply

current and may result in delays in transient response at

larger levels of overdrive.

Layout and Grounding

It is imperative that care is taken in PCB layout in order to

benefit from the very high speed and very low crosstalk of

the LT6555. Separate power and ground planes are highly

recommended and trace lengths should be kept as short

as possible. If input or output traces must be run over a

distance of several centimeters, they should use a con-

trolled impedance with matching series and shunt resis-

tances (nominally 75Ω) to maintain signal fidelity.

Series termination resistors should be placed as close to

the output pins as possible to minimize output capaci-

tance. See the Typical Performance Characteristics sec-

tion for a plot of frequency response with various output

capacitors—only 10pF of parasitic output capacitance

before the series termination resistor causes 6dB of

peaking in the frequency response!

Low ESL/ESR bypass capacitors should be placed as

close to the positive and negative supply pins as possible.

One 4700pF ceramic capacitor is recommended for both

and V

–

supply busses. Additional 470pF ceramic ca-

pacitors with minimal trace length on each supply pin will

further improve AC and transient response as well as

channel isolation. For high current drive and large-signal

transient applications, additional 1µF to 10µF tantalums

should be added on each supply. The smallest value

capacitors should be placed closest to the package.

If the AGND pins are not connected to ground, they must

be carefully bypassed to maintain minimal impedance

over frequency. Although crosstalk will vary depending

upon board layout, a recommended starting point for

bypass capacitors would be 470pF as close as possible to

each AGND pin with a single 4700pF capacitor in parallel.

REF

40k

6555 F01

–

Figure 1. Simplified Schematic of V

REF

Pin and Input Clamping

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LT6555IGN#PBF

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Video Switch ICs 650MHz Gain of 2 3x 2:1Video Multxer

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LT6555IGN#PBF

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