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VND5050AK-E
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P37
VND505
0AJ-E / VND50
50AK-E
Electrical sp
ecifica
tions
Doc ID 12
272 Rev 10
13/37
Figure 5.
Delay response time between rising edg
e of output current and rising
edge of cu
rrent se
nse (CS en
abled)
V
IN
I
OUT
I
SENSE
I
OUTMAX
I
SENSEMAX
90% I
SENSEMAX
90%
I
OUTMAX
Δ
t
DSENSE2H
t
t
t
Electric
al specific
ations
VND5050
AJ-E / VN
D5050AK-E
14/37
Do
c ID 122
72 Rev 10
Figure 6.
I
OUT
/I
SENSE
vs I
OUT
Figure 7.
Maximum current
sense r
atio drift vs load cur
rent
Note:
Param
eter guarant
eed by
design;
it is not
tested.
M
in -40°
C to
1
5
0°
C
M
ax
-4
0°
C t
o
1
5
0°
C
M
i
n 25°
C t
o
1
50°
C
Ma
x
2
5
°
C
t
o 1
5
0
°
C
Typ
25°
C
500
100
0
150
0
200
0
250
0
300
0
123
45
I
OUT
(A)
I
OUT
/I
SEN SE
-10
-5
0
5
10
12
34
I
OUT
(A)
dk/k
(%)
VND505
0AJ-E / VND50
50AK-E
Electrical sp
ecifica
tions
Doc ID 12
272 Rev 10
15/37
Figure 8.
Switching characteristics
Figure 9.
Output volt
age drop limit
a
tion
T
able 1
1.
T
ruth table
Conditions
In
put
Output
Sense (V
CSD
=0V)
(1)
1.
If the V
CSD
is high, the S
ENSE output is at
a high impedance, its pot
ential depends on leak
age currents
and external
circuit.
Normal operati
on
L
H
L
H
0
Nomi
nal
Over temper
ature
L
H
L
L
0
V
SENSEH
Undervo
ltage
L
H
L
L
0
0
Short ci
rcuit to GN
D
(R
sc
≤
10 m
Ω
)
L
H
H
L
L
L
0
0 if T
j
< T
TSD
V
SENSEH
if T
j
> T
TSD
Short ci
rcuit to V
CC
L
H
H
H
0
< Nominal
Negative o
utput vol
tag
e
clamp
LL
0
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10%
t
f
dV
OUT
/dt
(of
f)
t
d(off
)
t
d(on)
INP
UT
t
t
90%
t
Won
t
Woff
V
on
I
out
V
cc
-V
out
T
j
=150
o
C
T
j
=25
o
C
T
j
=-40
o
C
V
on
/R
on(T
)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P37
VND5050AK-E
Mfr. #:
Buy VND5050AK-E
Manufacturer:
STMicroelectronics
Description:
Power Switch ICs - Power Distribution Double Ch Hi Side Driver analog
Lifecycle:
New from this manufacturer.
Delivery:
DHL
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Ups
TNT
EMS
Payment:
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