Table 10: DDR2 I
DD
Specifications and Conditions – 4GB
Values shown for MT47H512M8THM DDR2 SDRAM only and are computed from values specified in the 4Gb TwinDie (512
Meg x 8) component data sheet
Parameter Symbol -800 -667 -53E Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC
(I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
I
DD0
TBD 904 824 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4, CL
= CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
puts are switching; Data pattern is same as I
DD4W
I
DD1
TBD 1264 944 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
I
DD2P
TBD 128 128 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
I
DD2Q
TBD 504 424 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
I
DD2N
TBD 584 504 mA
Active power-down current: All device banks open;
t
CK =
t
CK (I
DD
); CKE is LOW; Other control and address bus inputs are
stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
TBD 384 344 mA
Slow PDN exit
MR[12] = 1
TBD 144 144
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS
MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are switching
I
DD3N
TBD 544 464 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
I
DD4W
TBD 1304 1144 mA
Operating burst read current: All device banks open; Continuous burst read,
I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
I
DD4R
TBD 1464 1304 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
I
DD5
TBD 2344 2184 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
I
DD6
TBD 128 128 mA
Operating bank interleave read current: All device banks interleaving
reads; I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL =
t
RCD (I
DD
) - 1 ×
t
CK (I
DD
);
t
CK =
t
CK
(I
DD
),
t
RC =
t
RC (I
DD
),
t
RRD =
t
RRD (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
I
DD7
TBD 2824 2464 mA
2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
I
DD
Specifications
PDF: 09005aef821e5bf3
hts16c256_512x64h.pdf - Rev. E 3/10 EN
12
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© 2006 Micron Technology, Inc. All rights reserved.
