34
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
FEBRUARY 13, 2009
Figure 13. Read Cycle, Output Enable, Empty Flag and First Data Word Latency in Double Data Rate Mode (IDT Standard Mode)
NOTES:
1. t
SKEW2 is the minimum time between a falling WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the falling edge of WCLK and the rising edge of RCLK
is less than t
SKEW2, then EF deassertion may be delayed one extra RCLK cycle.
2. REN = LOW.
3. First data word latency = t
SKEW1 + 1*tRCLK + tREF.
4. RCS = LOW, WSDR = HIGH and RSDR = HIGH.
5. RCLK must be free running for EF to update.
t
OLZ
t
REF
t
REF
D
n
D
n
D
0
t
A
D
1
t
OHZ
t
OLZ
Q
0-
Q
39
EF
OE
WCLK
WEN
D
0
-D
39
5995 drw16
D
0
D
1
t
DH
t
DS
t
DS
t
DH
t
ENS
t
ENH
t
REF
t
A
RCLK
12
t
SKEW2
(1)
t
CLK2
t
CLKH2
t
OE
t
A
WCS
t
WCSS
t
WCSH
t
A
D
n
-
1
NO Read NO Read NO Read NO Read
t
CLKL2
