40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
FEBRUARY 13, 2009
Figure 19. Write Timing (FWFT Mode)
NOTES:
1. t
SKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than t
SKEW1, then OR assertion may be delayed one extra RCLK cycle.
2. t
SKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than t
SKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. D = 16,385 for IDT72T4088, 32,769 for IDT72T4098, 65,537 for IDT72T40108, 131,073 for IDT72T40118.
6. First data word latency = t
SKEW1 + 2*TRCLK + tREF.
W
1
W
2
W
4
W
[n +2]
W
[D-m-1]
W
[D-m-2]
W
[D-1]
W
D
W
[n+3]
W
[n+4]
W
[D-m]
W
[D-m+1]
WCLK
WEN
D0 - Dn
RCLK
t
DH
t
DS
t
SKEW1
(1)
REN
Q0 - Qn
PAF
PAE
IR
t
DS
t
DS
t
DS
t
SKEW2
t
A
t
REF
OR
t
PAES
t
PAFS
t
WFF
W
[D-m+2]
W
1
t
ENH
5995 drw22
PREVIOUS DATA IN OUTPUT REGISTER
(2)
W
3
1
2
3
1
D-1
2
+1
][
W
D-1
+2
][
W
2
D-1
+3
][
W
2
1
2
t
ENS
RCS
t
RCSLZ
t
ENS
