32
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
FEBRUARY 13, 2009
Figure 11. Write Cycle and Full Flag Timing in Double Data Rate Mode (IDT Standard Mode)
NOTES:
1. t
SKEW2 is the minimum time between a falling RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle plus tWFF). If the time between the falling edge of the RCLK and the rising edge of WCLK
is less than t
SKEW2, then FF deassertion may be delayed one extra WCLK cycle.
2. OE = LOW, EF = HIGH.
3. WCS = LOW, RCS = LOW, WSDR = HIGH and RSDR = HIGH.
4. WCLK must be free running for FF to update.
Data Read
Q
0
-Q39
5995 drw14
t
A
12
NO WRITE
D
0-
D39
RCLK
WCLK
WEN
FF
t
CLKL2
t
CLKH2
t
CLK2
t
SKEW2
(1)
12
t
SKEW2
(1)
REN
NO WRITE
Dx
t
DS
t
DS
t
DH
Dx+1
t
DH
Dx+2 Dx+3
t
WFF
t
WFF
t
WFF
t
WFF
t
ENH
t
ENS
t
ENH
t
ENS
t
A
Data in Output Register Next Data Read Next Data
t
A
t
A
Next Data Read
