38
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT
CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
FEBRUARY 13, 2009
Figure 17. Write Cycle and Full Flag in x40SDR to x20DDR with Bus-Matching and Rate-Matching (IDT Standard Mode)
WCLK
FF
WEN
RCS
t
ENS
Q0-Q19
RCLK
t
ENH
t
ENS
1
2
t
WFF
D0-D39
REN
t
RCSLZ
t
A
t
DS
t
DH
t
ENS
t
ENH
t
A
1
2
t
DS
t
DS
t
DH
t
DH
t
CLK1
NO WRITE
NO WRITE
t
WFF
DATA READ
NEXT DATA READ
Wx
Wx+2 Wx+3
t
A
t
DS
t
DH
Wx+1
t
CLKH1
t
CLKH1
t
WFF
t
A
t
SKEW2
(1)
t
WFF
t
ENS
t
RCSHZ
DATA
READ
NEXT DATA
READ
5995 drw20
t
SKEW2
(1)
NOTES:
1. t
SKEW2 is the minimum time between a falling RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle plus tWFF). If the time between the falling edge of the RCLK and the rising edge of WCLK
is less than t
SKEW2, then FF deassertion may be delayed one extra WCLK cycle.
2. OE = LOW, EF = HIGH.
3. WCS = LOW, RCS = LOW, WSDR = HIGH and RSDR = HIGH.
4. WCLK must be free running for FF to update.
