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EVK9FGV1004

P1-P3P4-P6P7-P9P10-P10
1©2018 Integrated Device Technology, Inc. March 1, 2018
Introduction
The evaluation board is designed to help the customer evaluate the 9FGV1001, 9FGV1002, and 9FGV1004 devices. When the board is
connected to a PC running IDT Timing Commander
™ software through USB, the device can be configured and programmed to generate
different combinations of frequencies.
Board Overview
Use Figure 1 and Table 1 to identify: power supply jacks, USB connector, input and output frequency SMA connectors.
Figure 1. Evaluation Board Overview
10
11
12
13
10
1
2
3
4
5
6
7
8
9
9FGV1001, 9FGV1002, and 9FGV1004
PhiClock™ PCIe Evaluation Board
User Guide
2©2018 Integrated Device Technology, Inc. March 1, 2018
9FGV1001, 9FGV1002, and 9FGV1004 PhiClock™ PCIe Evaluation Board User Guide
Board Power Supply
The evaluation board uses jumpers E1–E6 to set the power supply voltages for various V
DD
pins. The 4-way jumpers can select 3
different voltages from regulators that use power from the USB port. Selection #2 is the jack for connecting a bench power supply.
E1: Power supply for the REF outputs. The E1 voltage also determines the LVCMOS output levels of the REF0 and REF1 outputs.
E2: Power supply for the OUT0 output driver.
E3: Power supply for the OUT1 output driver.
E4: Power supply for the analog (V
DDA
) and digital (V
DDD
) core V
DD
pins.
E5: Power supply for the OUT2 output driver.
E6: Power supply for the OUT3 output driver.
See 9FGV100x Evaluation Board Schematics (Figure 5–Figure 8) for detailed information.
Table 1. Evaluation Board Pins and Functions
Label Number Name On-board Connector Label Function
1I
2
C Interface Connector J2
Alternative I
2
C interface connector for Aardvark.
IDT Timing Commander can also use Aardvark.
2 USB Connector J6
Connect this USB to your PC to run IDT Timing
Commander.
The board can be powered from the USB port.
3 Output Power Supply Jack J3
Connect to 1.8V, 2.5V or 3.3V for the output voltage of
the device.
4 Core Power Supply Jack J4
Connect to 1.8V, 2.5V or 3.3V for the core voltage of the
device.
5 Ground Jack J5 Connect to ground of power supply.
6 Differential Output 1 S7 and S10
Can be a differential pair, or two single-ended outputs.
Available logic types: LVCMOS, LVDS and LP-HCSL.
7 Differential Output 2 S6 and S9
Can be a differential pair, or two single-ended outputs.
Available logic types: LVCMOS, LVDS and LP-HCSL.
8 Differential Output 3 S5 and S8
Can be a differential pair, or two single-ended outputs.
Available logic types: LVCMOS, LVDS and LP-HCSL.
9 Reference Output 0 S1 Reference or buffered output from the crystal.
10
Power Supply Voltage
Selector
E1, E2, E3, E4, E5, E6
VDD_REFP1, VDDO_0, VDDO_1, four-way headers
used to select a power supply voltage. Connect the
center pin to one of the 4 surrounding pins to select a
voltage or a source.
11 Reference Output 1 S2 Reference or buffered output from the crystal.
12 Differential Output 0 S3 and S4
Can be a differential pair, or two single-ended outputs.
Available logic types: LVCMOS, LVDS and LP-HCSL.
13 DIP Switch U2
Used to control certain pins like OEA, OEB, SEL0, SEL1
and I
2
C versus Hardware Select mode.
3©2018 Integrated Device Technology, Inc. March 1, 2018
9FGV1001, 9FGV1002, and 9FGV1004 PhiClock™ PCIe Evaluation Board User Guide
DIP Switch (U2)
Refer to Figure 2 and Table 2 for the DIP switch settings and functions.
Figure 2. DIP Switch (U2)
Interfacing with a Computer to Run Timing Commander
As shown in Figure 3, jumpers JP1 and JP2 are installed to use the FTDI chip U6 for connecting to the computer with the USB port J6.
The U6 chip translates USB to I
2
C.
When using Aardvark, remove jumpers JP1 and JP2 and connect the Aardvark to connector J2. Default I
2
C device address for the
9FGV100x is 0x68.
Miscellaneous interfaces can connect to J2 pin 1 for the Serial Clock and to J2 pin 3 for the Serial Data signal. J2 pin 2 can be used as
ground, but any other ground pin will also work.
When OTP in the 9FGV100x devices is burned with multiple configurations, JP1 and JP2 can be applied in JP3 position respectively to
connect the SEL0 and SEL1 switches in U2. Move switch 8 to “+” and power-up the 9FGV100x in Hardware Select mode. This enables
changing between 4 configurations with SEL0/1.
Table 2. DIP Switch Settings
Switch Number Function
1 = OEA
See datasheet.
2 = OEB
3 = SEL0
Select 1 of 4 pre-programmed configurations when in Hardware Select mode. Also see switch 8.
4 = SEL1
5 Not used.
6 Not used.
7 Not used.
8 = Mode
Selects operating mode at power-up.
“-” or “O” selects I
2
C mode.
“+” selects Hardware Select mode.
P1-P3P4-P6P7-P9P10-P10

EVK9FGV1004

Mfr. #:
Buy EVK9FGV1004
Manufacturer:
IDT
Description:
Clock & Timer Development Tools EVK9FGV1004 EVAL KIT
Lifecycle:
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