ADP5588 Data Sheet
Rev. C | Page 6 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD MUST BE CONNECTED TO GROUND.
1R7
2R6
3R5
4R4
5R3
6R2
15 C6
16 C7
17 CMP_IN1/C8
18 CMP_IN2/C9
14 C5
13 C4
7
R1
8R0
9C0
11C2
12C3
10C1
21
V
CC
22
SDA
23
SCL
24
INT
20
RST
19
GND
TOP VIEW
(Not to Scale)
ADP5588
07673-003
Figure 3. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1 R7 GPIO, Row 7 in the Keypad Matrix.
2 R6 GPIO, Row 6 in the Keypad Matrix.
3 R5 GPIO, Row 5 in the Keypad Matrix.
4 R4 GPIO, Row 4 in the Keypad Matrix.
5 R3 GPIO, Row 3 in the Keypad Matrix.
6 R2 GPIO, Row 2 in the Keypad Matrix.
7 R1 GPIO, Row 1 in the Keypad Matrix.
8
R0
GPIO, Row 0 in the Keypad Matrix.
9 C0 GPIO, Column 0 in the Keypad Matrix.
10 C1 GPIO, Column 1 in the Keypad Matrix.
11 C2 GPIO, Column 2 in the Keypad Matrix.
12 C3 GPIO, Column 3 in the Keypad Matrix.
13 C4 GPIO, Column 4 in the Keypad Matrix.
14 C5 GPIO, Column 5 in the Keypad Matrix.
15 C6 GPIO, Column 6 in the Keypad Matrix.
16 C7 GPIO, Column 7 in the Keypad Matrix.
17 CMP_IN1/C8 GPIO, Column 8 in the Keypad Matrix; Comparator Input for Photosensor 1.
18 CMP_IN2/C9 GPIO, Column 9 in the Keypad Matrix; Comparator Input for Photosensor 2.
19 GND Ground.
20
RST
Hardware Reset (Active Low). This bit resets the device to the power default conditions. The reset pin must be
driven for a minimum of 50 μs to be valid and to prevent falsing due to ESD glitches or noise in the system. If
not used,
RST
must be tied high with a pull-up.
21 V
CC
V
CC
= 1.7 V to 3.3 V.
22 SDA I
2
C Serial Data (Open Drain Requires External Pull-up).
23
SCL
I
2
C Clock.
24
INT
Processor Interrupt, Active Low, Open Drain. This pin can be pulled up to 2.7 V or 1.8 V for selection flexibility in
the processor GPIO supply group.
EP EPAD Exposed Pad. The exposed pad must be connected to ground.
Data Sheet ADP5588
Rev. C | Page 7 of 28
THEORY OF OPERATION
CONTROL
REGISTERS
CONTROL
INTERFACE
REF
VOLTAGE
C9
C9
C8
C8
R7
R6
R5
R4
R3
R2
R1
R0
C0
C1
C2
C3
C4
C5
C6
C7
C9
C8
A0A1A2A3A4A5A6A7
B0B1B2B3B4B5B6B7
C0C1C2C3C4C5C6C7
D0D1D2D3D4D5D6D7
E0E1E2E3E4E5E6E7
F0F1F2F3F4F5F6F7
G0G1G2G3G4G5G6G7
H0H1H2H3H4H5H6H7
I0I1I2I3I4I5I6I7
J0J1J2J3J4J5J6J7
SCL
SDA
RST
INT
V
CC
GND
V
CC
SCL
SDA
19
21
23
22
18
17
20
24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
REF
VOLTAGE
0.1µF
0.1µF
V
CC
07673-009
ADP5588
RST
INT
Figure 4. Typical Operating Circuit
The ADP5588 is a GPIO expander that can be configured either
as an 18-I/O port expander or as a 10 column × 8 row keypad
matrix (80 keys maximum). It is ideal for cellular phone designs
and other portable devices that require a large extended keypad
and/or expanded I/Os (see the Applications Information section
for various configurations). When smaller size keypads are
required, unused GPIOs in the keypad matrix can be used as
I/Os (GPOs and GPIs). Two of the columns (C8 and C9) can
also be configured as comparator inputs for single or dual light
sensors. All GPIOs (rows and columns) default as GPIs at power-
up with pull-ups and debounce enabled.
KEYPAD OPERATION
Any number of rows and columns, up to 10 columns × 8 rows,
can be configured to be part of the keypad matrix. The rows
and columns that make up the keypad matrix must be con-
figured by setting the corresponding bits in Register 0x1D
through Register 0x1F. Keys on the keypad matrix appear on
the key event table with a decimal value of 1 (0x01 hexidecimal
or 0000001 binary) and run through 80 decimals (0x50 hexi-
decimal or 1010000 binary). See Table 10 for key event number
assignments. The keypad, in idle mode, is configured with
columns being driven low and rows as inputs high with pull-ups.
Table 10. Key Event Number Assignment Table
Row C0 C1 C2 C3 C4 C5 C6 C7 C8 C9
R0
1 2 4 4 5 6 7 8 9 10
R1
11 12 13 14 15 16 17 18 19 20
R2
21
22
23
24
25
26
27
28
29
30
R3
31 32 33 34 35 36 37 38 39 40
R4
41 42 43 44 45 46 47 48 49 50
R5
51
52
53
54
55
56
57
58
59
60
R6
61 62 63 64 65 66 67 68 69 70
R7
71 72 73 74 75 76 77 78 79 80
When one key press or multiple key presses (short between
coumn and row) occur, the internal state machine checks the
row pins to determine which one is driven low and then triggers
an interrupt. The state machine then starts a key scan cycle to
determine which keys are pressed. After a key has been pressed
for 25 ms, the state machine sets the appropriate key(s) in the
key event status register with the key-pressed bits set (the MSB
in the key event register) in the order detected. If the KE_IEN
field in Register 0x01 is set, the state machine then sets the
KE_INT field in Register 0x01 and generates an interrupt to the
host processor.
ADP5588 Data Sheet
Rev. C | Page 8 of 28
To prevent glitches or narrow press times registering as valid
key presses, the key scanner requires the key to be pressed for
two scan cycles. The key scanner has a sampling period of 25 ms,
so the key must be pressed and held for at least 25 ms to register
as pressed. If the key is continuously pressed, the key scanner
continues to sample every 25 ms. If a key that was pressed is
released for 25 ms or greater, the state machine sets the appro-
priate keys in the key event status register with the key pressed
bits cleared in the order detected. Because the release of a key is
not necessarily in sync with the key scan sampling period, it may
take between 25 ms and 50 ms for a key to register as released.
After the key is registered as released, the key scanner goes back
to idle mode. Figure 5 shows the row and column pins
connected to a typical 10 × 8, 80-switch keypad matrix.
KEYPAD SCAN AND DECODE
D0_PULL
J7
I7
H7
G7
F7
E7
D7
C7
B7
A7
J6
I6
H6
G6
F6
E6
D6
C6
B6
A6
J5
I5
H5
G5
F5
E5
D5
C5
B5
A5
J4
I4
H4
G4
F4
E4
D4
C4
B4
A4
J3
I3
H3
G3
F3
E3
D3
C3
B3
A3
J2
I2
H2
G2
F2
E2
D2
C2
B2
A2
J1
I1
H1
G1
F1
E1
D1
C1
B1
A1
J0
I0
H0
G0
F0
E0
D0
C0
B0
A0
R7 R6 R5 R4 R3 R2 R1
R0
C0 C1 C2 C3 C4 C5 C6 C7 C9C8
10 × 8 KEYPAD MATRIX
V
CC
D1_PULL
D2_PULL
D3_PULL
D4_PULL
D5_PULL
D6_PULL
D7_PULL
07673-010
Figure 5. Keypad Decode Configuration
Key Event Tracking
The 10-key event registers are set to act as a FIFO, meaning that
reading any of the 10-key event registers yields the key events in
the order they were pressed and released.
Tracking of key events is done with the help of the key event
counter (the KEC field in Register 0x03) and the FIFO/key
event registers (Register 0x04 through Register 0x0D). The KEC
count increases as keys are pressed and released; up to 10 events
can be logged in the counter. The FIFO/key event registers, on
the other hand, display the key events and their status (pressed
or released) as they are read out of the FIFO. The FIFO registers
are made of eight bits, with the MSB dedicated as the status bit
(1 indicates a press and 0 indicates a release); the remaining
seven bits are used to display binary representation of the keys
that are pressed or released.
The first read of any of the FIFO registers displays the first
event that happened and its status. Subsequent reads of the
same register replace the register data with the next event that
happens. If tracking of all the events is important, it is best to
used a single register per event. After all the events in the FIFO
are read, reading of any of the event registers yields a zero value.
Table 11 and Table 12 show the event sequences as they are
logged in and read from the FIFO. The 10 FIFO registers are
labeled A through J, and keys are labeled A0 through J7.
Table 11. Example of Event Sequence
Key Pressed/Released Status Key Event Counter
A0 Pressed 1
B1 Pressed 2
A0 Released 3
C2 Pressed 4
B1 Released 5
D3 Pressed 6
C2 Released 7
E4 Pressed 8
E4
Released
9
D3 Released 10
Table 12. Interpretation of FIFO Event Reading
Key Event
Counter
Key Event
Register
Read
Key Event Reg-
ister Content
(Binary)
1
Key Event
Register
Interpretation
10 N/A N/A N/A
9 D 1 0000001 Key A0 pressed
8 E 1 0001100 Key B1 pressed
7
C
0 0000001
Key A0 released
6 F 1 0010111 Key C2 pressed
5 G 0 0001100 Key B1 released
4 A 1 0100010 Key D3 pressed
3 B 0 0010111 Key C2 released
2 H 1 0101101 Key E4 pressed
1 J 0 0101101 Key E4 released
0 I 0 0100010 Key D3 released
1
The first number indicates a key press or key release in Bit 7 of the key event
register: 1 = key press; 0 = key release.
Key Event Overflow
The ADP5588 is equipped with an overflow feature to handle
key events beyond the FIFO capacity. When all events are filled, any
additional events set the OVR_FLOW_INT bit in Register 0x02;
if the OVR_FLOW_IEN bit in Register 0x01 is set, the host
processor is also interrupted when overflow occurs. When the
FIFO is not full, new events are added as the last events.
The OVR_FLOW_M bit in Register 0x01 sets the mode of
operation during overflows. Clearing the OVR_FLOW_M bit
causes new incoming events to be discarded, and setting this bit
rolls over and overwrites old data with new data starting at the
first event.

ADP5588ACPZ-R7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Interface - I/O Expanders QWERTY Keypad Cntlr
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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