3-4
converter is approximately 1.5V. Therefore, the duty cycle of
the sampling clock should be measured at the 1.5V trigger
level of the HI5767 sample clock input pin.
The sinewave to logic level comparator drives a series of
additional inverters that provide isolation between the three
sample clocks used on the evaluation board. One clock is
used to drive the converter sample clock input pin and the
other two provide CLK and
CLK at the data output
header/connector, P2. The clock/data relationship at the P2
output connector is as follows. CLK has rising edges aligned
with digital data transitions and
CLK has rising edges
aligned mid-bit.
The data corresponding to a particular analog input sample
will be available at the digital outputs of the HI5767 after the
data latency (7 cycles) plus the HI5767 digital data output
delay.
The sample clock and digital output data signals are made
available through two connectors contained on the evaluation
board. Line drivers are not provided for the digital output data
and it should be pointed out that the load presented to the
converter digital output data signals, D0 - D9, should not
exceed the data sheet CMOS drive limits and a load
capacitance of 10pF. The P1 96-pin I/O connector allows the
evaluation board to be interfaced to the DSP evaluation
boards available from Intersil. The digital output data and
sample clock can also be accessed by clipping the test leads
of a logic analyzer or data acquisition system onto the
header/connector pins of connector P2.
The A/D converters
OE control input pin allows the digital
output data bus of the converter to be switched to a three-
state high impedance mode. This feature enables the testing
and debugging of systems which are utilizing one or more
converters. This three-state control signal is not intended for
use as an enable/disable function on a common data bus
and could result in possible bus contention issues. The A/D
converters
OE control input pin is controlled by the
installation or removal of a shunt, JP1, contained on the
evaluation board. Installation of JP1 forces the
OE control
input pin low for normal operation while removal of JP1
allows the digital output data bus of the converter to be
switched to a three-state high impedance mode.
HI5767 Performance Characterization
Dynamic testing is used to evaluate the performance of the
HI5767 A/D converter. Among the tests performed are
Signal-to-Noise and Distortion Ratio (SINAD), Signal-to-
Noise Ratio (SNR), Total Harmonic Distortion (THD),
Spurious Free Dynamic Range (SFDR) and Intermodulation
Distortion (IMD).
Figure 4 shows the test system used to perform dynamic
testing on high-speed ADCs at Intersil. The clock (CLK) and
analog input (V
IN
) signals are sourced from low phase noise
HP8662A synthesized signal generators that are phase
locked to each other to ensure coherence. The output of the
signal generator driving the ADC analog input is bandpass
filtered to improve the harmonic distortion of the analog input
signal. The comparator on the evaluation board will convert
the sine wave CLK input signal to a square wave at TTL logic
levels to drive the sample clock input of the HI5767. The
ADC data is captured by a logic analyzer and then
transferred over the GPIB bus to the PC. The PC has the
required software to perform the Fast Fourier Transform
(FFT) and do the data analysis.
Coherent testing is recommended in order to avoid the
inaccuracies of windowing. The sampling frequency and
analog input frequency have the following relationship: f
I
/f
S
=
M/N, where f
I
is the frequency of the input analog sinusoid,
f
S
is the sampling frequency, N is the number of samples,
and M is the number of cycles over which the samples are
taken. By making M an integer and odd number (1, 3, 5, ...)
the samples are assured of being nonrepetitive.
Refer to the HI5767 data sheet for a complete list of test
definitions and the results that can be expected using the
evaluation board with the test setup shown. Evaluating the
part with a reconstruction DAC is only suggested when
doing bandwidth or video testing.
HP8662A
HP8662A
FILTER
BANDPASS
HI5767EVAL2
PC
HI5767
COMPARATOR
REF
V
IN
CLK
DIGITAL DATA OUTPUT
14
GPIB
DAS9200
EVALUATION BOARD
V
IN
CLK
FIGURE 3. HIGH-SPEED A/D PERFORMANCE TEST SYSTEM
Application Note 9762
