Preliminary Rev. 0.26 7/07 Copyright © 2007 by Silicon Laboratories Si5325
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5325
µP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
Description
The Si5325 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5325 accepts dual clock inputs ranging
from 10 to 710 MHz and generates two clock outputs ranging
from 10 to 945 MHz and select frequencies to 1.4 GHz. The
two outputs are divided down separately from a common
source. The device provides virtually any frequency
translation combination across this operating range. The
Si5325 input clock frequency and clock multiplication ratio
are programmable through an I
2
C or SPI interface. The
Si5325 is based on Silicon Laboratories' 3rd-generation
DSPLL
®
technology, which provides any-rate frequency
synthesis in a highly integrated PLL solution that eliminates
the need for external VCXO and loop filter components. The
DSPLL loop bandwidth is digitally programmable, providing
jitter performance optimization at the application level.
Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5325
is ideal for providing clock multiplication in high performance
timing applications
.
Applications
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Optical modules
Wireless basestations
Data converter clocking
xDSL
SONET/SDH + PDH clock synthesis
Test and measurement
Features
Generates any frequency from 10 to 945 MHz and
select frequencies to 1.4 GHz from an input
frequency of 10 to 710 MHz
Low jitter clock outputs w/jitter generation as low as
0.6 ps rms (30 kHz–1.3 MHz)
Integrated loop filter with selectable loop bandwidth
(150 kHz to 2 MHz)
Dual clock inputs w/manual or automatically
controlled hitless switching
Dual clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 and custom FEC ratios
(255/238, 255/237, 255/236)
LOS, FOS alarm outputs
Digitally-controlled output phase adjust
I
2
C or SPI programmable
On-chip voltage regulator for 1.8, 2.5, or 3.3 V
±10% operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
PRELIMINARY DATA SHEET
DSPLL
®
CKOUT2
CKIN1
CKOUT1
CKIN2
÷ N31
÷ N2
÷ NC1
÷ NC2
Signal Detect
Device Interrupt
VDD (1.8, 2.5, or 3.3 V)
GND
÷ N32
Clock Select
I
2
C/SPI Port
Control
Alarms
