SI5325B-B-GM Datasheet SI5325C-B-GM, SI5325A-B-GM, SI5325B-B-GM | P7-P9

Si5325

Preliminary Rev. 0.26 7

4C2BOLVCMOSCKIN2 Invalid Indicator.

This pin functions as a LOS (and optionally FOS) alarm indi-

cator for CKIN2 if CK2_BAD_PIN

=1.

0 = CKIN2 present.

1 = LOS (FOS) on CKIN2.

The active polarity can be changed by CK_BAD_POL

. If

CK2_BAD_PIN

= 0, the pin tristates.

5, 10, 11,

15, 32

Supply Supply.

The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass

capacitors should be associated with the following Vdd pins:

5 0.1 µF

10 0.1 µF

32 0.1 µF

A 1.0 µF should be placed as close to device as is practical.

6, 8, 31

GND

GND Supply Ground.

Must be connected to system ground. Minimize the ground

path impedance for optimal performance of this device.

CKIN2+

CKIN2–

IMultiClock Input 2.

Differential input clock. This input can also be driven with a

single-ended signal. Input frequency range is 10 to 710 MHz.

CKIN1+

CKIN1–

IMultiClock Input 1.

Differential input clock. This input can also be driven with a

single-ended signal. Input frequency range is 10 to 710 MHz.

21 CS_CA I/O LVCMOS Input Clock Select/Active Clock Indicator.

In manual clock selection mode, this pin functions as the

manual input clock selector if the CKSEL_PIN

is set to 1.

0 = Select CKIN1.

1 = Select CKIN2.

If CKSEL_PIN

=0, the CKSEL_REG register bit controls this

function and this input tristates.

In automatic clock selection mode, this pin indicates which of

the two input clocks is currently the active clock. If alarms

exist on both clocks, CA will indicate the last active clock that

was used before entering the digital hold state. The

CK_ACTV_PIN

active clock status to the CA output pin.

0 = CKIN1 active input clock.

1 = CKIN2 active input clock.

If CK_ACTV_PIN

= 0, this pin will tristate. The CA status will

always be reflected in the CK_ACTV_REG

read only register

bit.

Table 3. Si5325 Pin Descriptions (Continued)

Pin # Pin Name I/O Signal Level Description

Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map.

Si5325

8 Preliminary Rev. 0.26

22 SCL I LVCMOS Serial Clock/Serial Clock.

This pin functions as the serial clock input for both SPI and

C modes.

23 SDA_SDO I/O LVCMOS Serial Data.

In I

C control mode (CMODE = 0), this pin functions as the

bidirectional serial data port.

In SPI control mode (CMODE = 1), this pin functions as the

serial data output.

ILVCMOSSerial Port Address.

In I

C control mode (CMODE = 0), these pins function as

hardware controlled address bits.

In SPI control mode (CMODE = 1), these pins are ignored.

26 A2_S

S ILVCMOSSerial Port Address/Slave Select.

In I

C control mode (CMODE = 0), this pin functions as a

hardware controlled address bit.

In SPI control mode (CMODE = 1), this pin functions as the

slave select input.

27 SDI I LVCMOS Serial Data In.

In I

C control mode (CMODE = 0), this pin is ignored.

In SPI control mode (CMODE = 1), this pin functions as the

serial data input.

CKOUT1–

CKOUT1+

OMultiOutput Clock 1.

Differential output clock with a frequency range of 10 MHz to

1.4175 GHz. Output signal format is selected by

SFOUT1_REG

LVPECL, LVDS, and CML compatible modes. For CMOS for-

mat, both output pins drive identical single-ended clock out-

puts.

CKOUT2–

CKOUT2+

OMultiOutput Clock 2.

Differential output clock with a frequency range of 10 MHz to

1.4175 GHz. Output signal format is selected by

SFOUT2_REG

LVPECL, LVDS, and CML compatible modes. For CMOS for-

mat, both output pins drive identical single-ended clock out-

puts.

36 CMODE I LVCMOS Control Mode.

Selects I

C or SPI control mode for the Si5325.

0 = I

C Control Mode.

1 = SPI Control Mode.

GND PAD GND GND Supply Ground Pad.

The ground pad must provide a low thermal and electrical

impedance to a ground plane.

Table 3. Si5325 Pin Descriptions (Continued)

Pin # Pin Name I/O Signal Level Description

Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map.

Si5325

Preliminary Rev. 0.26 9

3. Ordering Guide

Ordering Part

Number

Output Clock Frequency

Range

Package Temperature Range

Si5325A-B-GM 10–945 MHz

970–1134 MHz

1.213–1.417 GHz

36-Lead 6 x 6 mm QFN –40 to 85 °C

Si5325B-B-GM 10–808 MHz 36-Lead 6 x 6 mm QFN –40 to 85 °C

Si5325C-B-GM 10–346 MHz 36-Lead 6 x 6 mm QFN –40 to 85 °C

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

SI5325B-B-GM

Mfr. #:

Buy SI5325B-B-GM

Manufacturer:

Silicon Labs

Description:

IC UP-PROG CLK MULTIPLIER 36QFN

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SI5325B-B-GM

SI5325B-B-GM

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