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74LVC574APW,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
74LVC574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 18 December 2012 9 of 19
NXP Semiconductors
74LVC574A
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
11. AC waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times, and the
maximum frequency
mna802
CP
input
Qn
output
t
PHL
t
PLH
t
W
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 8. Data set-up and hold times for the Dn input to the CP input
mna803
GND
GND
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
I
V
OH
V
OL
V
I
Qn output
CP input
Dn input
74LVC574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 18 December 2012 10 of 19
NXP Semiconductors
74LVC574A
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 9. 3-state enable and disable times
mna80
t
PLZ
t
PHZ
outputs
disabled
outputs
enable
V
Y
V
X
outputs
enabled
Q
n
output
LOW-to-OFF
OFF-to-LOW
Q
n
output
HIGH-to-OFF
OFF-to-HIGH
OE input
V
OL
V
OH
V
CC
V
I
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
I
V
M
V
M
V
X
V
Y
1.2 V V
CC
0.5 V
CC
0.5 V
CC
V
OL
+ 0.15 V V
OH
0.15 V
1.65 V to 1.95 V V
CC
0.5 V
CC
0.5 V
CC
V
OL
+ 0.15 V V
OH
0.15 V
2.3 V to 2.7 V V
CC
0.5 V
CC
0.5 V
CC
V
OL
+ 0.15 V V
OH
0.15 V
2.7 V 2.7 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
0.3 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
0.3 V
74LVC574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 18 December 2012 11 of 19
NXP Semiconductors
74LVC574A
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
Test data is given in Table 9.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 10. Test circuitry for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
C
L
R
T
R
L
R
L
G
Table 9. Test data
Supply voltage Input Load V
EXT
V
I
t
r
, t
f
C
L
R
L
t
PLH
, t
PHL
t
PLZ
, t
PZL
t
PHZ
, t
PZH
1.2 V V
CC
2 ns 30 pF 1 k open 2 V
CC
GND
1.65 V to 1.95 V V
CC
2 ns 30 pF 1 k open 2 V
CC
GND
2.3 V to 2.7 V V
CC
2 ns 30 pF 500 open 2 V
CC
GND
2.7V 2.7V 2.5 ns 50 pF 500 open 2 V
CC
GND
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open 2 V
CC
GND
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74LVC574APW,112

Mfr. #:
Buy 74LVC574APW,112
Manufacturer:
Nexperia
Description:
Flip Flops 3.3V OCTAL D FF POS
Lifecycle:
New from this manufacturer.
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