1. General description
The 74HC194 is a 4-bit bidirectional universal shift register. The synchronous operation of
the device is determined by the mode select inputs (S0, S1). In parallel load mode (S0
and S1 HIGH) data appearing on the D0 to D3 inputs, when S0 and S1 are HIGH, is
transferred to the Q0 to Q3 outputs. When S0 is HIGH and S1 is LOW data is entered
serially via DSL and shifted from left to right; when S0 is LOW and S1 is HIGH data is
entered serially via DSR and shifted from right to left. DSR and DSL allow multistage shift
right or shift left data transfers without interfering with parallel load operation. If both S0
and S1 are LOW, existing data is retained in a hold mode. Mode select and data inputs
are edge-triggered, responding only to the LOW-to-HIGH transition of the clock (CP).
Therefore, the only timing restriction is that the mode control and selected data inputs
must be stable one set-up time prior to the positive transition of the clock pulse. When
LOW, the asynchronous master reset (MR
) overrides all other input conditions and forces
the Q outputs LOW. Inputs include clamp diodes. This enables the use of current limiting
resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC194: CMOS level
Shift-left and shift right capability
Synchronous parallel and serial data transfer
Easily expanded for both serial and parallel operation
Asynchronous master reset
Hold (‘do nothing’) mode
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and 40 C to +125 C
74HC194
4-bit bidirectional universal shift register
Rev. 3 — 29 November 2016 Product data sheet
