74HC194 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 29 November 2016 7 of 17
NXP Semiconductors
74HC194
4-bit bidirectional universal shift register
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
t
pd
propagation
delay
CP to Qn; see Figure 8
[1]
V
CC
= 2.0 V - 47 145 - 180 - 220 ns
V
CC
= 4.5 V - 17 29 - 36 - 44 ns
V
CC
= 5.0 V; C
L
=15pF - 14 - - - - - ns
V
CC
= 6.0 V - 14 25 - 31 - 38 ns
t
PHL
High to LOW
propagation
delay
MR to Qn; see Figure 9
V
CC
= 2.0 V - 39 140 - 175 - 210 ns
V
CC
= 4.5 V - 14 28 - 35 - 42 ns
V
CC
= 5.0 V; C
L
=15pF - 11 - - - - - ns
V
CC
= 6.0 V - 11 24 - 30 - 36 ns
t
t
transition
time
see Figure 8
[2]
V
CC
= 2.0 V - 19 75 - 95 - 110 ns
V
CC
=4.5V - 7 15 - 19 - 22 ns
V
CC
=6.0V - 6 13 - 16 - 19 ns
t
W
pulse width CP HIGH or LOW; see Figure 8
V
CC
= 2.0 V 80 17 - 100 - 120 - ns
V
CC
=4.5V 16 6 - 20 - 24 - ns
V
CC
=6.0V 14 5 - 17 - 20 - ns
t
W
pulse width MR pulse width LOW;
see Figure 9
V
CC
= 2.0 V 80 17 - 100 - 120 - ns
V
CC
=4.5V 16 6 - 20 - 24 - ns
V
CC
=6.0V 14 5 - 17 - 20 - ns
t
rec
recovery
time
MR to CP; see Figure 9
V
CC
=2.0V 60 17 - 75 - 90 - ns
V
CC
=4.5V 12 6 - 15 - 18 - ns
V
CC
=6.0V 10 5 - 13 - 15 - ns
74HC194 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 29 November 2016 8 of 17
NXP Semiconductors
74HC194
4-bit bidirectional universal shift register
t
su
set-up time Dn to CP; see Figure 10
V
CC
= 2.0 V 70 17 - 90 - 105 - ns
V
CC
=4.5V 14 6 - 18 - 21 - ns
V
CC
=6.0V 12 5 - 15 - 18 - ns
S0, S1 to CP; see Figure 11
V
CC
= 2.0 V 80 22 - 100 - 120 - ns
V
CC
=4.5V 16 8 - 20 - 24 - ns
V
CC
=6.0V 12 6 - 17 - 20 - ns
DSR, DSL to CP;
see Figure 10
V
CC
= 2.0 V 70 19 - 90 - 105 - ns
V
CC
=4.5V 14 7 - 18 - 21 - ns
V
CC
=6.0V 12 6 - 15 - 18 - ns
t
h
hold time Dn to CP; see Figure 10
V
CC
=2.0V 0 14 - 0 - 0 - ns
V
CC
=4.5V 0 5- 0 - 0 - ns
V
CC
=6.0V 0 4- 0 0 - ns
S0, S1 to CP; see Figure 11
V
CC
=2.0V 0 11 - 0 - 0 - ns
V
CC
=4.5V 0 4- 0 - 0 - ns
V
CC
=6.0V 0 3- 0 0 - ns
DSR, DSL to CP;
see Figure 10
V
CC
=2.0V 0 17 - 0 - 0 - ns
V
CC
=4.5V 0 6- 0 - 0 - ns
V
CC
=6.0V 0 5- 0 0 - ns
f
max
maximum
frequency
CP; see Figure 8
V
CC
=2.0V 6 31 - 4.8 - 4 - MHz
V
CC
=4.5V 30 93 - 24 - 20 - MHz
V
CC
= 5.0 V; C
L
=15pF - 102 - - - - - MHz
V
CC
=6.0V 35 111 - 28 - 24 - MHz
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC194 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 29 November 2016 9 of 17
NXP Semiconductors
74HC194
4-bit bidirectional universal shift register
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
11. Waveforms
C
PD
power
dissipation
capacitance
V
I
= GND to V
CC
; f
i
=1MHz
[3]
-40- - - - - pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
Logic levels V
OL
and V
OH
are typical output voltage
levels that occur with the output load.
Measurement points are given in Table 8
.
Logic levels V
OL
and V
OH
are typical output voltage
levels that occur with the output load.
Fig 8. The clock (CP) to output (Qn) propagation
delays, the clock pulse width, the output
transition times and the maximum clock
frequency
Fig 9. The master reset (MR) pulse width, master
reset to output (Qn) propagation delays, and
the master reset to clock (CP) recovery times
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3
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Q
RXWSXW
9
0
9
0
I
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:
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3+/
W
3/+
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7+/
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7/+
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

DDD
9
,
*1'
*1'
9
,
9
2+
9
2/
9
0
9
0
9
0
9
0
W
:
W
UHF
W
3+/
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74HC194D,652

Mfr. #:
Manufacturer:
Nexperia
Description:
Counter Shift Registers 4-BIT BIDIR SHFT REG
Lifecycle:
New from this manufacturer.
Delivery:
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