LTC4002
13
4002f
Input and Output Capacitors
Since the input capacitor is assumed to absorb all input
switching ripple current in the converter, it must have an
adequate ripple current rating. Worst-case RMS ripple cur-
rent is approximately one-half of output charge current.
Actual capacitance value is not critical. Solid tantalum
capacitors have a high ripple current rating in a relatively
small surface mount package, but caution must be used
when tantalum capacitors are used for input bypass. High
input surge currents can be created when the adapter is
hot-plugged to the charger and solid tantalum capacitors
have a known failure mechanism when subjected to very
high turn-on surge currents. Selecting the highest pos-
sible voltage rating on the capacitor will minimize prob-
lems. Consult with the manufacturer before use.
The selection of output capacitor C
OUT
is primarily deter-
mined by the ESR required to minimize ripple voltage and
load step transients. The output ripple V
OUT
is approxi-
mately bounded by:
∆≤ +
V I ESR
fC
OUT L
OSC OUT
1
8
Since I
L
increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
APPLICATIO S I FOR ATIO
WUUU
Switching ripple current splits between the battery and the
output capacitor depending on the ESR of the output ca-
pacitor and the battery impedance. EMI considerations
usually make it desirable to minimize ripple current in the
battery leads. Ferrite beads or an inductor may be added
to increase battery impedance at the 500kHz switching
frequency. If the ESR of the output capacitor is 0.2 and
the battery impedance is raised to 4 with a bead or induc-
tor, only 5% of the current ripple will flow in the battery.
Design Example
As a design example, take a charger with the following
specifications: V
IN
= 5V to 22V, V
BAT
= 4V nominal, I
BAT
=
1.5A, f
OSC
= 500kHz, see Figure 2.
First, calculate the SENSE resistor :
R
SENSE
= 100mV/1.5A = 68m
Choose the inductor for about 65% ripple current at the
maximum V
IN
:
L
V
kHz A
V
V
H=
()()()
4
500 0 65 1 5
1
4
22
6 713
..
–.
Selecting a standard value of 6.8µH results in a maximum
ripple current of :
=
()
µ
()
=I
V
kHz H
V
V
mA
L
4
500 6 8
1
4
22
962 6
.
–.
LTC4002
14
4002f
APPLICATIO S I FOR ATIO
WUUU
Next, choose the P-channel MOSFET. The Si6435ADQ in
a TSSOP-8 package with R
DS(ON)
= 42m (nom), 55m
(max) offers a small solution. The maximum power dissi-
pation with V
IN
= 5V and V
BAT
= 4V at 50°C ambient
temperature is:
P
AmV
V
W
D
=
()
()()
=
1 5 55 4
5
0 099
2
.
.
T
J
= 50°C + (0.099W)(65°C/W) = 56.5°C
C
IN
is chosen for an RMS current rating of about 0.8A at
85°C. The output capacitor is chosen for an ESR similar to
the battery impedance of about 100m. The ripple voltage
on the BAT pin is:
V
I ESR
A
mV
OUT RIPPLE
LMAX
()
()
..
=
()
=
()
()
=
2
096 01
2
48
C1: Taiyo Yuden TMK325BJ106MM
C2: Taiyo Yuden JMK325BJ226MM
L1: TOKO B952AS-6R8N
The Schottky diode D2 shown in Figure 2 conducts current
when the pass transistor is off. In a low duty cycle case, the
current rating should be the same or higher than the
charge current. Also it should withstand reverse voltage as
high as V
IN
.
Board Layout Suggestions
When laying out the printed circuit board, the following
considerations should be taken to ensure proper opera-
tion of the LTC4002.
GATE pin rise and fall times are 20ns and 50ns respectively
(with C
GATE
= 2000pF). To minimize radiation, the catch
diode, pass transistor and the input bypass capacitor
traces should be kept as short as possible. The positive
side of the input capacitor should be close to the source of
the P-channel MOSFET; it provides the AC current to the
pass transistor. The connection between the catch diode
and the pass transistor should also be kept as short as
possible. The SENSE and BAT pins should be connected
directly to the sense resistor (Kelvin sensing) for best
charge current accuracy. Avoid routing the NTC PC board
trace near the MOSFET switch to minimize coupling switch-
ing noise into the NTC pin.
The compensation capacitor connected at the COMP pin
should return to the ground pin of the IC or as close to it
as possible. This will prevent ground noise from disrupt-
ing the loop stability. The ground pin also works as a heat
sink, therefore use a generous amount of copper around
the ground pin. This is especially important for high V
CC
and/or high gate capacitance applications.
L1
6.8µH
+
4002 F02
NTC: DALE NTHS-1206N02
C
C
0.47µF
R
C
2.2k
4.2V
Li-Ion
BATTERY
10k
NTC
SENSE
GATE
BAT
CHRG
LTC4002ES8-4.2
V
CC
V
IN
5V TO 22V
BAT
NTC GND
COMP
R1
2k
CHARGE
STATUS
T
M1
Si6435ADQ
2
3
7
61
5
48
D1
B330
D2
B330
C2
22µF
CER
C1
10µF
CER
C3
0.1µF
CER
R
SENSE
68m
Figure 2. 1.5A Single Cell Li-Ion Battery Charger
LTC4002
15
4002f
U
PACKAGE DESCRIPTIO
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1103
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)
×
45
°
0
°
– 8
°
TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1
2
3
4
.150 – .157
(3.810 – 3.988)
NOTE 3
8
7
6
5
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN
.160
±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC4002ES8-4.2#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management St&alone Li-Ion Switch Mode Bat Chr
Lifecycle:
New from this manufacturer.
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