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M48T86 Operation
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2 Operation
The M48T86 clock is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed 23 ppm (parts per million) oscillator
frequency error at 25°C, which equates to approximately ±1 minute per month. Automatic
deselection of the device ensures the data integrity is not compromised should V
CC
fall
below specified power-fail deselect voltage (V
PFD
) levels (see Figure 14 on page 27). The
automatic deselection of the device remains in effect upon power up for a period of 200ms
(max) after V
CC
rises above V
PFD
, provided that the real-time clock is running and the count-
down chain is not reset. This allows sufficient time for V
CC
to stabilize and gives the system
clock a wake-up period so that a valid system reset can be established.
The block diagram in Figure 4 on page 8 shows the pin connections and the major internal
functions of the M48T86.
2.1 Signal description
2.1.1 V
CC
, V
SS
DC power is provided to the device on these pins.The M48T86 uses a 5 V V
CC
.
2.1.2 SQW (square wave output)
During normal operation (e.g., valid V
CC
), the SQW pin can output a signal from one of 13
taps. The frequency of the SQW pin can be changed by programming Register A as shown
in Table 4 on page 18. The SQW signal can be turned on and off using the SQWE bit
(Register B; Bit 3). The SQW signal is not available when V
CC
is less than V
PFD
.
2.1.3 AD0-AD7 (multiplexed bidirectional address/data bus)
The M48T86 provides a multiplexed bus in which address and data information share the
same signal path. The bus cycle consists of two stages; first the address is latched, followed
by the data. Address/Data multiplexing does not slow the access time of the M48T86,
because the bus change from address to data occurs during the internal RAM access time.
Addresses must be valid prior to the falling edge of AS (see Figure 5 on page 11), at which
time the M48T86 latches the address present on AD0-AD7. Valid WRITE data must be
present and held stable during the latter portion of the R/W
pulse (see Figure 6 on page 11).
In a READ cycle, the M48T86 outputs 8 bits of data during the latter portion of the DS pulse.
The READ cycle is terminated and the bus returns to a high impedance state upon a high
transition on R/W
.
2.1.4 AS (address strobe input)
A positive going pulse on the Address Strobe (AS) input serves to demultiplex the bus. The
falling edge of AS causes the address present on AD0-AD7 to be latched within the
M48T86.
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