LTC3824
10
3824fh
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applicaTions inForMaTion
Inductor Selection
The maximum inductor current is determined by :
I
L(MAX)
=I
OUT(MAX)
+
I
RIPPLE
2
where I
RIPPLE
=
(V
IN
V
OUT
) D
f L
and Duty Cycle D =
V
OUT
+ V
D
V
IN
+ V
D
V
D
is the catch diode D1 forward voltage and f is the
switching frequency.
A small inductance will result in larger ripple current,
output ripple voltage and also larger inductor core loss.
An empirical starting point for the inductor ripple current
is about 40% of maximum DC current.
L =
(V
IN
V
OUT
) D
f 0.4 I
OUT(MAX)
The saturation current level of the inductor should be
sufficiently larger than I
L(MAX)
.
Power MOSFET Selection
Important parameters for the power MOSFET include the
drain-to-source breakdown voltage (BV
DSS
), the threshold
voltage (V
GS(TH)
), the on-resistance (R
DS(ON)
) versus gate-
to-source voltage, the gate-to-source and gate-to-drain
charges (Q
GS
and Q
GD
, respectively), the maximum drain
current (I
D(MAX)
) and the MOSFETs thermal resistance
(R
TH(JC)
) and R
TH(JA)
.
The gate drive voltage is set by the 8V internal regulator.
Consequently, at least 10V V
GS
rated MOSFETs are required
in high voltage applications.
In order to calculate the junction temperature of the power
MOSFET, the power dissipated by the device must be known.
This power dissipation is a function of the duty cycle, the
load current and the junction temperature itself (due to the
positive temperature coefficient of R
DS(ON)
)
.
The power
dissipation calculation should be based on the worst-cast
specifications for V
SENSE(MAX)
, the required load current at
maximum duty cycle, the voltage and temperature ranges,
and the R
DS(ON)
of the MOSFET listed in the data sheet.
The power dissipated by the MOSFET when the LTC3824
is in continuous mode is given by :
P
MOSFET
=
V
OUT+
V
D
V
IN
+ V
D
(I
OUT
)
2
(1+ δ)R
DS(ON)
+ K(V
IN
)
2
(I
OUT
)(C
RSS
)(f)
The first term in the equation represents the I
2
R losses in
the device and the second term is the switching losses. K
(estimated as 1.7) is an empirical factor inversely related
to the gate drive current and has the unit of 1/Amps. The δ
term accounts for the temperature coefficient of the R
DS(ON)
of the MOSFET, which is typically 0.4%/°C. C
RSS
is the
MOSFET reverse transfer capacitance. Figure 1 illustrates
the variation of normalized R
DS(ON)
over temperature for
a typical power MOSFET.
Figure 1. Normalized R
DS(ON)
vs Temperature
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
T
J
= T
A
+ P
MOSFET
R
TH(JA)
The R
TH(JA)
to be used in this equation normally includes
the R
TH(JC)
for the device plus the thermal resistance from
the case to the ambient temperature (R
TH(CA)
). This value
of T
J
can then be compared to the original assumed value
used in the calculation.
Output Diode Selection
The catch diode carries load current during the switch
off-time. The average diode current is therefore dependent
JUNCTION TEMPERATURE (°C)
–50
δ NORMALIZED ON-RESISTANCE
1.0
1.5
150
3824 F01
0.5
0
0
50
100
2.0
LTC3824
11
3824fh
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on the P-channel switch duty cycle. At high input voltages
the diode conducts most of the time. As V
IN
approaches
V
OUT
the diode conducts only a small fraction of the time.
The worst condition for the diode is when the output is
shorted to ground. Under this condition the diode must
safely handle the maximum current at close to 100% of
the time. Therefore, the diode must be carefully chosen
to meet the worst case voltage and current requirements.
Under normal conditions, the average current conducted
by the diode is:
I
D
= I
OUT
(1 – D)
A fast switching Schottky diode must be used to optimize
efficiency.
C
IN
and C
OUT
Selection
A low ESR input capacitor, C
IN
, sized for the maximum
RMS P-channel switch current is required to prevent large
input voltage transients. The maximum RMS capacitor
current is given by:
I
RMS
=I
OUT(MAX)
V
OUT
V
IN
V
IN
V
OUT
1
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
=
I
OUT
/2. This simple worst-case condition is commonly used
for design because even significant deviations do not offer
much relief. Note that ripple current ratings from capacitor
manufacturers are often based on only 2000 hours of life
which makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
size or height requirements in the design.
The selection of C
OUT
is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable.
The output ripple, V
OUT
, is determined by:
ΔV
OUT
ΔI
L
ESR+
1
8fC
OUT
The output ripple is highest at maximum input voltage
since I
L
increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR, but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long-term reliability. Ceramic capaci
-
tors have excellent low ESR characteristics but can have
a high voltage coefficient and audible noise.
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power
. Percentage efficiency
can be expressed as:
% Efficiency = 100%–(L1 + L2 + L3 +......)
where L1, L2, L3...are the individual loss components as a
percentage of the input power. It is often useful to analyze
individual losses to determine what is limiting the efficiency
and which change would produce the most improvement.
Although all dissipative elements in the circuit produce
losses, the following are the main sources:
1. The supply current into V
CC
. The V
CC
current is the sum
of the DC supply current and the MOSFET driver and
control currents. The DC supply current into the V
CC
pin
is typically about 1mA. The driver current results from
switching the gate capacitance of the power MOSFET;
this current is typically much larger than the DC current.
Each time the MOSFET is switched on and off, a packet
of gate charge Q
G
is transferred from the CAP pin to
V
CC
throughout the external bypass capacitor, C
CAP
.
The resulting dQ/dt is a current that must be supplied
to the capacitor by the internal regulator.
I
Q
= 1mA + f Q
G
P
IC
= V
IN
I
Q
LTC3824
12
3824fh
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2. Power MOSFET switching and conduction losses:
P
MOSFET
=
V
OUT
+
V
D
V
IN
+ V
D
(I
OUT
)
2
(1+ δ)R
DS(ON)
+ K(V
IN
)
2
(I
OUT
)(C
RSS
)(f)
3. The I
2
R losses of the current sense resistor:
P
(SENSE R)
= (I
OUT
)
2
R D
where D is the duty cycle
4. The inductor loss due to winding resistance:
P
(WINDING)
= (I
OUT
)
2
R
W
5. Loss of the catch diode:
P
(DIODE)
= I
OUT
V
D
(1–D)
6. Other losses, including C
IN
and C
OUT
ESR dissipation
and inductor core losses, generally account for less
than 2% of total losses.
PCB Layout Considerations
To achieve best performance from a LTC3824 circuit, the PC
board layout must be carefully designed. For lower power
applications, a 2-layer PC board is sufficient. However, at
higher power levels, a multiple layer PC board is recom
-
mended. Using a solid ground plane under the circuit is
the easiest way to ensure that switching noise does not
affect the operation.
In
order to
help dissipate the power from the MOSFET and
diode, keep the ground plane on the layers closest to the
layers where power components are mounted. Use power
planes for the MOSFET and diode in order to improve the
spreading of heat from these components into the PCB.
For best electrical performance the LTC3824 circuit should
be laid out as following:
Place all power components in a tight area. This will
minimize the size of high current loops. Orient the input
and output capacitors and current sense resistor in a way
that minimizes the distance between the pads connected
to ground plane.
Place the LTC3824 and associated components tightly
together and next to the section with power components.
Use a local via to ground plane for all pads that connect to
ground. Use multiple vias for power components.
Connect the current sense input directly to the current
sense resistor pad. V
CC
and SENSE are the inputs of the
internal current sense amplifier and should be connected
as close to the sense resistor pads as possible. A 100pF
capacitor is required across the V
CC
and sense pins for
noise filtering and should be placed as close to the pins
as possible.
Design Example
As an example, the LTC3824 is designed for an automo
-
tive 5V power supply with the following specifications:
Maximum I
OUT
= 2A, typical V
IN
= 6V to 18V and can reach
60V briefly during load dump condition, and operating
switching frequency = 400kHz.
For f = 400kHz, R
SET
is chosen to be 180k.
Allow inductor ripple current to be 0.8A (40% of the
maximum output current) at V
IN
= 18V,
L =
(18V 5V)5V
(400kHz 0.8A)18V
= 12μH
C
OUT
will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. For this design
a 220µF tantalum capacitor is used.
For worse-case conditions C
IN
should be rated for at least
1A ripple current (half of the maximum output current). A
47µF tantalum capacitor is adequate.
A current limit of 3.3A is selected and R
SENSE
can be
calculated by :
R
SENSE
=
100mV
3.3A
= 0.03Ω
and a 25mΩ resistor can be used.

LTC3824MPMSE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators High Voltage Step-Down Controller With 40uA Quiescent Current
Lifecycle:
New from this manufacturer.
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