©2011 Silicon Storage Technology, Inc. DS25080A 11/11
11
2 Mbit SPI Serial Flash
SST25LF020A
Not Recommended for New Designs
Microchip Technology Company
High-Speed-Read (33 MHz)
The High-Speed-Read instruction supporting up to 33 MHz is initiated by executing an 8-bit command,
0BH, followed by address bits [A
23
-A
0
] and a dummy byte. CE# must remain active low for the duration
of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy byte (8 clocks input dummy cycle), the High-Speed-Read instruction outputs the
data starting from the specified address location. The data output stream is continuous through all
addresses until terminated by a low to high transition on CE#. The internal address pointer will auto-
matically increment until the highest memory address is reached. Once the highest memory address is
reached, the address pointer will automatically increment to the beginning (wrap-around) of the
address space, i.e. for 2 Mbit density, once the data from address location 03FFFFH has been read,
the next output will be from address location 000000H.
Figure 6: High-Speed-Read Sequence
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A
23
-A
0
]. Following the address, the data is
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status register or wait T
BP
for the completion of
the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence.
Figure 7: Byte-Program Sequence
1242 F05.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.0B
HIGH IMPEDANCE
15 16 23 24 31 32 39 40
47 48 55 56 63 64
N+2 N+3 N+4
N
N+1
X
MSB
MSB
MSB
MODE 0
MODE 3
D
OUT
D
OUT
D
OUT
D
OUT
80
71 72
D
OUT
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
IL
or V
IH
)
1242 F06.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD. D
IN
02
HIGH IMPEDANCE
15 16
23
24
31
32
39
MODE 0
MODE 3
MSBMSB
MSB
LSB