CY7C1011CV33 Automotive
2-Mbit (128 K × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-86374 Rev. *C Revised April 17, 2015
2-Mbit (128 K × 16) Static RAM
Features
■ Temperature ranges
❐ Automotive-E: –40 °C to 125 °C
■ High speed
❐ t
AA
= 10 ns
■ Low active power
❐ 468 mW (max)
■ 2.0 V data retention
■ Automatic power down when deselected
■ Independent control of upper and lower bits
■ Easy memory expansion with Chip Enable (CE) and Output
Enable (OE
) features
■ Available in Pb-free 48-ball grid array (BGA) package
Functional Description
The CY7C1011CV33 Automotive is a high performance
complementary metal oxide semiconductor (CMOS) static RAM
organized as 131,072 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
To write to the device, take CE
and Write Enable (WE) inputs
LOW. If Byte Low Enable (BLE
) is LOW, then data from I/O pins
(I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
16
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
16
).
To read from the device, take CE and OE LOW while forcing the
Write Enable (WE
) HIGH. If BLE is LOW, then data from the
memory location specified by the address pins appear on I/O
0
to
I/O
7
. If Byte High Enable (BHE) is LOW, then data from memory
appears on I/O
8
to I/O
15
. For more information, see the Truth
Table on page 10 for a complete description of Read and Write
modes.
The input and output pins (I/O
0
through I/O
15
) are placed in a
high impedance state when the device is deselected (CE
HIGH),
the outputs are disabled (OE
HIGH), the BHE and BLE are
disabled (BHE
, BLE HIGH), or during a write operation (CE LOW
and WE
LOW).
For a complete list of related resources, click here.
128 K x 16
RAM Array
I/O
0
–I/O
7
ROW DECODER
A
0
A
1
A
2
A
3
A
6
COLUMN DECODER
A
10
A
11
A
12
A
13
A
14
SENSE AMPS
INPUT BUFFER
OE
A
4
A
5
I/O
8
–I/O
15
WE
BLE
BHE
A
15
A
8
A
7
A
16
CE
A
9
Logic Block Diagram
