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NLX1G74MUTCG

P1-P3P4-P6
NLX1G74
http://onsemi.com
4
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0 ns)
Symbol Parameter V
CC
(V) Test Conditions
T
A
= 25°C T
A
= −40 to 85°C
Unit
Min Typ Max Min Max
f
MAX
Maximum Clock
Frequency
(50% Duty Cycle)
(Waveform 1)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
75 75
MHz
2.5 ± 0.2 150 150
3.3 ± 0.3 200 200
5.0 ± 0.5 250 250
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
175 175
5.0 ± 0.5 200 200
t
PLH
,
t
PHL
Propagation Delay,
CP to Q or Q
(Waveform 1)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
2.5 6.5 12.5 2.5 13
ns
2.5 ± 0.2 1.5 3.8 7.5 1.5 8.0
3.3 ± 0.3 1.0 2.8 6.5 1.0 7.0
5.0 ± 0.5 0.8 2.2 4.5 0.8 5.0
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
1.0 3.4 7.0 1.0 7.5
5.0 ± 0.5 1.0 2.6 5.0 1.0 5.5
t
PLH
,
t
PHL
Propagation Delay,
PR
or CLR to Q or Q
(Waveform 2)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
2.5 6.5 14 2.5 14.5
ns
2.5 ± 0.2 1.5 3.8 9.0 1.5 9.5
3.3 ± 0.3 1.0 2.8 6.5 1.0 7.0
5.0 ± 0.5 0.8 2.2 5.0 0.8 5.5
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
1.0 3.4 7.0 1.0 7.5
5.0 ± 0.5 1.0 2.6 5.0 1.0 5.5
t
S
Setup Time, D to CP
(Waveform 1)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
6.5 6.5
ns
2.5 ± 0.2 3.5 3.5
3.3 ± 0.3 2.0 2.0
5.0 ± 0.5 1.5 1.5
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
2.0 2.0
5.0 ± 0.5 1.5 1.5
t
H
Hold Time, D to CP
(Waveform 1)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
0.5 0.5
ns
2.5 ± 0.2 0.5 0.5
3.3 ± 0.3 0.5 0.5
5.0 ± 0.5 0.5 0.5
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
0.5 0.5
5.0 ± 0.5 0.5 0.5
t
W
Pulse Width,
CP, CLR
, PR
(Waveform 3)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
6.0 6.0
ns
2.5 ± 0.2 4.0 4.0
3.3 ± 0.3 3.0 3.0
5.0 ± 0.5 2.0 2.0
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
3.0 3.0
5.0 ± 0.5 2.0 2.0
t
REC
Recover Time
PR
; CLR to CP
(Waveform 3)
1.8 ± 0.15
C
L
= 15 pF
R
D
= 1 MW
S
1
= Open
8.0 8.0
MHz
2.5 ± 0.2 4.5 4.5
3.3 ± 0.3 3.0 3.0
5.0 ± 0.5 3.0 3.0
3.3 ± 0.3
C
L
= 50 pF,
R
D
= 500 W, S
1
= Open
3.0 3.0
5.0 ± 0.5 3.0 3.0
7. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/ 2 (per flip−flop). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
CAPACITANCE (Note 8)
Symbol
Parameter Condition Typical Unit
C
IN
Input Capacitance V
CC
= 5.5 V 7.0 pF
C
OUT
Output Capacitance V
CC
= 5.5 V 7.0 pF
C
PD
Power Dissipation Capacitance (Note 9)
Frequency = 10 MHz
V
CC
= 3.3 V
V
CC
= 5.0 V
16
21
pF
8. T
A
= +25°C, f = 1 MHz
9. C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I
CCD
) at
no output loading and operating at 50% duty cycle. (See Figure 1) C
PD
is related to I
CCD
dynamic operating current by the expression:
I
CCD
= C
PD
V
CC
f
in
+ I
CC(static)
.
NLX1G74
http://onsemi.com
5
t
rec
WAVEFORM 3 − RECOVERY TIME
t
R
= t
F
= 3.0 ns from 10% to 90%; f = 1 MHz; t
w
= 500 ns
Output Reg: V
OL
≤ 0.8 V, V
OH
≥ 2.0 V
Vcc
0 V
Vcc
0 V
50%
50%
Figure 1. AC Waveforms
WAVEFORM 2 − PROPAGATION DELAYS
t
R
= t
F
= 3.0 ns, 10% to 90%; f = 1 MHz; t
W
= 500 ns
PR
, CLR
CP
Vcc
0 V
PR
CLR
50%
Q
Vcc
0 V
V
OH
50%
Q
V
OL
50%
50%
50%
t
PLH
t
PHL
t
PHL
t
PLH
WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES
t
R
= t
F
= 3.0 ns, 10% to 90%; f = 1 MHz; t
W
= 500 ns
Vcc
0 V
D
CP
50%
Q,
Q
Vcc
0 V
V
OH
V
OL
t
PLH
, t
PHL
t
h
t
s
50%
50%
f
max
t
w
t
w
t
w
50%
PULSE
GENERATOR
R
T
DUT
V
CC
R
L
C
L
Figure 2. Test Circuit
NLX1G74
http://onsemi.com
6
PACKAGE DIMENSIONS
UQFN8
MU SUFFIX
CASE 523AN
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
A
B
E
D
BOTTOM VIEW
b
e
8X
0.10 B
0.05
AC
C
NOTE 3
2X
0.10 C
PIN ONE
REFERENCE
TOP VIEW
2X
0.10 C
A
A1
(A3)
0.05 C
0.05 C
C
SEATING
PLANE
SIDE VIEW
L
8X
1
3
5
8
DIM MIN MAX
MILLIMETERS
A 0.45 0.60
A1 0.00 0.05
A3 0.13 REF
b 0.15 0.25
D 1.60 BSC
L1 −−− 0.15
E 1.60 BSC
e 0.50 BSC
L 0.35 0.45
L1
DETAIL A
A1
A3
DETAIL B
OPTIONAL
MOLD CMPD
EXPOSED Cu
b
CONSTRUCTION
OPTIONAL
CONSTRUCTION
DETAIL B
DETAIL A
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
PITCH
0.35
7X
DIMENSIONS: MILLIMETERS
1
7
L3
0.25
1.70
1.70
0.50
L3 0.25 0.35
L3
(0.10)
(0.15)
8X
0.53
8X
0.53
8X
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particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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PUBLICATION ORDERING INFORMATION
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Phone: 81−3−5817−1050
NLX1G74/D
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NLX1G74MUTCG

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Flip Flops SINGLE D FLIP FLOP
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