AT28C64B-15JU Datasheet AT28C64B-15TU-T, AT28C64B-15JU-T, AT28C64B-15SU-T | P1-P3

Features

• Fast Read Access Time – 150 ns

• Automatic Page Write Operation

– Internal Address and Data Latches for 64 Bytes

• Fast Write Cycle Times

– Page Write Cycle Time: 10 ms Maximum (Standard)

2 ms Maximum (Option – Ref. AT28HC64BF Datasheet)

– 1 to 64-byte Page Write Operation

• Low Power Dissipation

– 40 mA Active Current

– 100 µA CMOS Standby Current

• Hardware and Software Data Protection

• DATA Polling and Toggle Bit for End of Write Detection

• High Reliability CMOS Technology

– Endurance: 100,000 Cycles

– Data Retention: 10 Years

• Single 5V ±10% Supply

• CMOS and TTL Compatible Inputs and Outputs

• JEDEC Approved Byte-wide Pinout

• Industrial Temperature Ranges

• Green (Pb/Halide-free) Packaging Option Only

1. Description

The AT28C64B is a high-performance electrically-erasable and programmable read-

only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits.

Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers

access times to 150 ns with power dissipation of just 220 mW. When the device is

deselected, the CMOS standby current is less than 100 µA.

The AT28C64B is accessed like a Static RAM for the read or write cycle without the

need for external components. The device contains a 64-byte page register to allow

writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to

64 bytes of data are internally latched, freeing the address and data bus for other

operations. Following the initiation of a write cycle, the device will automatically write

the latched data using an internal control timer. The end of a write cycle can be

detected by DATA

POLLING of I/O7. Once the end of a write cycle has been

detected, a new access for a read or write can begin.

Atmel’s AT28C64B has additional features to ensure high quality and manufacturabil-

ity. The device utilizes internal error correction for extended endurance and improved

data retention characteristics. An optional software data protection mechanism is

available to guard against inadvertent writes. The device also includes an extra

64 bytes of EEPROM for device identification or tracking.

64K (8K x 8)

Parallel

EEPROM with

Page Write and

Software Data

Protection

AT28C64B

0270L–PEEPR–2/09

AT28C64B

2. Pin Configurations

2.1 28-lead PDIP, 28-lead SOIC Top View

Pin Name Function

A0 - A12 Addresses

CE Chip Enable

Output Enable

Write Enable

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

DC Don’t Connect

A12

I/O0

I/O1

I/O2

GND

VCC

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

2.2 32-lead PLCC Top View

Note: PLCC package pins 1 and 17 are Don’t Connect.

2.3 28-lead TSOP Top View

I/O0

A11

A10

I/O7

I/O6

I/O1

I/O2

GND

I/O3

I/O4

I/O5

A12

VCC

A11

VCC

A12

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

0270L–PEEPR–2/09

AT28C64B

3. Block Diagram

4. Device Operation

4.1 Read

The AT28C64B is accessed like a Static RAM. When CE and OE are low and WE is high, the

data stored at the memory location determined by the address pins is asserted on the outputs.

The outputs are put in the high-impedance state when either CE

or OE is high. This dual line

control gives designers flexibility in preventing bus contention in their systems.

4.2 Byte Write

A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write

cycle. The address is latched on the falling edge of CE

or WE, whichever occurs last. The data is

latched by the first rising edge of CE

or WE. Once a byte write has been started, it will automati-

cally time itself to completion. Once a programming operation has been initiated and for the

duration of t

, a read operation will effectively be a polling operation.

4.3 Page Write

The page write operation of the AT28C64B allows 1 to 64 bytes of data to be written into the

device during a single internal programming period. A page write operation is initiated in the

same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63

additional bytes. Each successive byte must be loaded within 150 µs (t

BLC

) of the previous byte.

If the t

BLC

limit is exceeded, the AT28C64B will cease accepting data and commence the internal

programming operation. All bytes during a page write operation must reside on the same page

as defined by the state of the A6 to A12 inputs. For each WE

high to low transition during the

page write operation, A6 to A12 must be the same.

The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be

loaded in any order and may be altered within the same load period. Only bytes which are spec-

ified for writing will be written; unnecessary cycling of other bytes within the page does not occur.

VCC

GND

ADDRESS

INPUTS

X DECODER

Y DECODER

OE, CE and WE

LOGIC

DATA INPUTS/OUTPUTS

I/O0 - I/O7

DATA LATCH

INPUT/OUTPUT

BUFFERS

Y-GATING

CELL MATRIX

IDENTIFICATION

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

AT28C64B-15JU

Mfr. #:

Buy AT28C64B-15JU

Manufacturer:

Microchip Technology / Atmel

Description:

EEPROM 64K 8K x 8 150 ns 4.5V-5.5V

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AT28C64B-15JU

AT28C64B-15JU

Products related to this Datasheet