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0270L–PEEPR–2/09
AT28C64B
4.4 DATA Polling
The AT28C64B features DATA Polling to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will result in the complement of the written
data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all
outputs, and the next write cycle may begin. DATA
Polling may begin at any time during the write
cycle.
4.5 Toggle Bit
In addition to DATA Polling, the AT28C64B provides another method for determining the end of a
write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling, and valid data will be read. Toggle bit reading may begin at any time during the write cycle.
4.6 Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel
®
has incorporated both hardware and software features that will protect the
memory against inadvertent writes.
4.6.1 Hardware Data Protection
Hardware features protect against inadvertent writes to the AT28C64B in the following ways: (a)
V
CC
sense – if V
CC
is below 3.8 V (typical), the write function is inhibited; (b) V
CC
power-on delay
– once V
CC
has reached 3.8 V, the device will automatically time out 5 ms (typical) before allow-
ing a write; (c) write inhibit – holding any one of OE
low, CE high, or WE high inhibits write
cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE
or CE inputs will not ini-
tiate a write cycle.
4.6.2 Software Data Protection
A software controlled data protection feature has been implemented on the AT28C64B. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C64B is shipped from Atmel with SDP dis-
abled.
SDP is enabled by the user issuing a series of three write commands in which three specific
bytes of data are written to three specific addresses (see “Software Data Protection Algorithms”
on page 10). After writing the 3-byte command sequence and waiting t
WC
, the entire AT28C64B
will be protected against inadvertent writes. It should be noted that even after SDP is enabled,
the user may still perform a byte or page write to the AT28C64B by preceding the data to be writ-
ten by the same 3-byte command sequence used to enable SDP.
Once set, SDP remains active unless the disable command sequence is issued. Power transi-
tions do not disable SDP, and SDP protects the AT28C64B during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not actually written into the device; their
addresses may still be written with user data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device. However, for the duration of
t
WC
, read operations will effectively be polling operations.
4.7 Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-
ing A9 to 12V ±0.5V and using address locations 1FC0H to 1FFFH, the additional bytes may be
written to or read from in the same manner as the regular memory array.
