OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD7366BRUZ-5500RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
AD7366-5/AD7367-5
Rev. B | Page 19 of 28
DRIVER AMPLIFIER CHOICE
Each AD7366-5/AD7367-5 has a total of four analog inputs,
which operate in single-ended mode. Both ADC analog inputs
can be programmed to one of the three analog input ranges. In
applications where the signal source is high impedance, it is
recommended to buffer the signal before applying it to the
ADC analog inputs. Figure 21 shows the configuration of the
AD7366-5/AD7367-5 in single-ended mode.
In applications where the THD and SNR are critical specifi-
cations, the analog input of the AD7366-5/AD7367-5 should be
driven from a low impedance source. Large source impedances
significantly affect the ac performance of the ADC and can
necessitate the use of an input buffer amplifier.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of THD that can be tolerated
in the application. The THD increases as the source impedance
increases and performance degrades. Figure 7 shows THD vs.
the analog input frequency for various source impedances.
Depending on the input range and analog input configuration
selected, the AD7366-5/AD7367-5 can handle source
impedances as illustrated in Figure 7.
Due to the programmable nature of the analog inputs on the
AD7366-5/AD7367-5, the choice of op amp used to drive the
inputs is a function of the particular application and depends
on the selected analog input voltage ranges.
The driver amplifier must be able to settle for a full-scale step to
a 14-bit level, 0.0061%, in less than the specified acquisition time
of the AD7366-5/AD7367-5. An op amp such as the AD8021
meets this requirement when operating in single-ended mode.
The AD8021 needs an external compensating NPO type of
capacitor. The AD8022 can also be used in high frequency
applications where a dual version is required. For lower frequency
applications, recommended op amps are the AD797, AD845,
and AD8610.
V
+
V–
V
DD
V
SS
V
A1
DV
CC
/AV
CC
+5V
AGND
AD8021
1k
1k
15pF
C
COMP
= 10pF
–10V/–5V
+10V/+5V
AD7366-5/
AD7367-5*
*ADDITIONAL PINS OMITTED FOR CLARITY.
10µF
+
0.1µF
+
0.1µF
+
+
10µF
+
06842-023
Figure 21. Typical Connection Diagram with the AD8021
Driving the Analog Input in Single-Ended Mode
V
DRIVE
The AD7366-5/AD7367-5 also have a V
DRIVE
feature to control
the voltage at which the serial interface operates. V
DRIVE
allows
the ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7366-5/AD7367-5 is operated with a V
CC
of
5 V, the V
DRIVE
pin could be powered from a 3 V supply, allowing
a large dynamic range with low voltage digital processors. Thus,
the AD7366-5/AD7367-5 could be used with the ±10 V input
range while still being able to interface to 3 V digital parts.
REFERENCE
The AD7366-5/AD7367-5 can operate with either the internal
2.5 V on-chip reference or an externally applied reference. The
logic state of the REFSEL pin determines whether the internal
reference is used. The internal reference is selected for both ADCs
when the REFSEL pin is tied to logic high. If the REFSEL pin is
tied to GND, an external reference can be supplied through the
D
CAP
A and D
CAP
B pins. On power-up, the REFSEL pin must be
tied to either a low logic or high logic state for the part to operate.
Suitable reference sources for the AD7366-5/AD7367-5 include
the AD780, AD1582, ADR431, REF193, and ADR391.
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When operating the AD7366-5/
AD7367-5 in internal reference mode, the 2.5 V internal reference
is available at the D
CAP
A and D
CAP
B pins, which should be
decoupled to AGND using a 680 nF capacitor. It is recommended
that the internal reference be buffered before applying it elsewhere
in the system. The internal reference is capable of sourcing up
to 150 A with an analog input range of ±10 V and 70 µA for
both the ±5 V range and 0 V to +10 V range
If the internal reference operation is required for the ADC
conversion, the REFSEL pin must be tied to logic high on power-
up. The reference buffer requires 70 µs to power up and charge
the 680 nF decoupling capacitor during the power-up time.
The AD7366-5/AD7367-5 is specified for a 2.5 V to 3 V reference
range. When a 3 V reference is selected, the ranges are ±12 V,
±6 V, and 0 V to +12 V. For these ranges, the V
DD
and V
SS
supply
must be greater than or equal to the +12 V and −12 V, respectively.
AD7366-5/AD7367-5
Rev. B | Page 20 of 28
MODES OF OPERATION
The mode of operation for the AD7366-5/AD7367-5 is selected
by the (logic) state of the
CNVST
signal at the end of a conver-
sion. There are two possible modes of operation: normal mode
and shutdown mode. These modes of operation are designed to
provide flexible power management options, which can be
chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
NORMAL MODE
Normal mode is intended for applications needing fast
throughput rates because the user does not have to worry
about any power-up times (with the AD7366-5/AD7367-5
remaining fully powered at all times). Figure 22 shows the
normal mode of operation for the AD7366-5, while Figure 23
illustrates normal mode for the AD7367-5.
The conversion is initiated on the falling edge of
CNVST
as
described in the section. To ensure that
the part remains fully powered up at all times,
Circuit Information
CNVST
must be
at a logic high state prior to the BUSY signal going low. If
CNVST
is at a logic low state when the BUSY signal goes low,
the analog circuitry powers down and the part ceases converting.
The BUSY signal remains high for the duration of the conversion.
The
CS
pin must be brought low to bring the data bus out of
three-state; subsequently 12 SCLK cycles are required to read
the conversion result from the AD7366-5, while 14 SCLK cycles
are required to read from the AD7367-5. The D
OUT
lines return
to three-state only when
CS
is brought high. If
CS
is left low for
a further 12 SCLK cycles for the AD7366-5 or 14 SCLK cycles
for the AD7367-5, the result from the other on-chip ADC is
also accessed on the same D
OUT
line, as shown in and
(see the section).
Figure 27
Figure 28 Serial Interface
After 24 SCLK cycles have elapsed for the AD7366-5 and 28 SCLK
cycles have elapsed for the AD7367-5, the D
OUT
line returns to
three-state when
CS
is brought high (not on the 24
th
or 28
th
SCLK
falling edge). If
CS
is brought high prior to this, the D
OUT
line
returns to three-state at that point. Thus,
CS
must be brought
high once the read is completed because the bus does not
automatically return to three-state upon completion of the
dual result read.
Once a data transfer is complete and D
OUT
A and D
OUT
B have
returned to three-state, another conversion can be initiated after
the quiet time, t
QUIET
, has elapsed by bringing
CNVST
low again.
CNVST
BUSY
SCLK
t
2
t
1
t
3
SERIAL READ OPERATION
CS
1
12
t
CONVERT
t
QUIET
06842-024
Figure 22. Normal Mode Operation for the AD7366-5
BUSY
SCLK
t
2
t
1
t
3
SERIAL READ OPERATION
CS
1
14
t
CONVERT
t
QUIET
CNVST
06842-025
Figure 23. Normal Mode Operation for the AD7367-5
AD7366-5/AD7367-5
Rev. B | Page 21 of 28
SHUTDOWN MODE
Shutdown mode is intended for use in applications where slow
throughput rates are required. Shutdown mode is suited to
applications where a series of conversions performed at a
relatively high throughput rate are followed by a long period of
inactivity and, thus, shutdown. When the AD7366-5/AD7367-5
are in full power-down, all analog circuitry is powered down.
The falling edge of
CNVST
initiates the conversion. The BUSY
output subsequently goes high to indicate that the conversion is
in progress. Once the conversion is completed, the BUSY output
returns low. If the
CNVST
signal is at logic low when BUSY
goes low, the part enters shutdown at the end of the conversion
phase. While the part is in shutdown mode, the digital output
code from the last conversion on each ADC can still be read
from the D
OUT
pins. To read the D
OUT
data,
CS
must be brought
low as described in the section. The D
OUT
pins
return to three-state once
Serial Interface
CS
is brought back to logic high.
To exit full power-down and to power up the AD7366-5/
AD7367-5, a rising edge of
CNVST
is required. After the
required power-up time has elapsed,
CNVST
may be brought
low again to initiate another conversion, as shown in Figure 24
POWER-UP TIMES
As described in the Shutdown Mode section, the AD7366-5/
AD7367-5 have one power-down mode. This section deals with
the power-up time required when coming out of this mode. It
should be noted that these power-up times apply with the
recommended capacitors in place on the D
CAP
A and D
CAP
B pins.
To power up from shutdown,
CNVST
must be brought high and
remain high for a minimum of 70 s, as shown in . Figure 24
When power supplies are first applied to the AD7366-5/AD7367-5,
the ADC can power up with
CNVST
in either the low or high
logic state. Before attempting a valid conversion,
CNVST
must
be brought high and remain high for the recommended power-
up time of 70 s.
CNVST
can then be brought low to initiate a
conversion. With the AD7366-5/AD7367-5, no dummy conversion
is required before valid data can be read from the
D
OUT
pins.
If it is intended to place the part in shutdown mode when the
supplies are first applied, the AD7366-5/AD7367-5 must be
powered up, and a conversion initiated. However,
CNVST
should remain in the logic low state, and when the BUSY signal
goes low, the part enters shutdown.
Once supplies are applied to the AD7366-5/AD7367-5, sufficient
time must be allowed for any external reference to power up
and to charge the various reference buffer decoupling capacitors
to their final values.
BUSY
SCLK
SERIAL READ OPERATION
CS
1
12
t
CONVERT
t
3
t
2
ENTERS SHUTDOWN
t
POWER-UP
CNVST
06842-026
Figure 24. Autoshutdown Mode for AD7366-5
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

AD7366BRUZ-5500RL7

Mfr. #:
Buy AD7366BRUZ-5500RL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Bipolar Input Dual 12B 2Ch SAR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet