AD7366-5/AD7367-5
Rev. B | Page 27 of 28
APPLICATION HINTS
LAYOUT AND GROUNDING
The printed circuit board that houses the AD7366-5/AD7367-5
should be designed so that the analog and digital sections are
confined to their own separate areas of the board. This design
facilitates the use of ground planes that can be easily separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally the best option. All AGND pins on
the AD7366-5/AD7367-5 should be connected to the AGND
plane. Digital and analog ground pins should be joined in only
one place. If the AD7366-5/AD7367-5 are in a system where
multiple devices require an AGND and DGND connection, the
connection should still be made at only one point. A star point
should be established as close as possible to the ground pins on
the AD7366-5/AD7367-5.
Good connections should be made to the power and ground
planes. This can be done with a single via or multiple vias for
each supply and ground pin.
Avoid running digital lines under the AD7366-5/AD7367-5
devices because this couples noise onto the die. However, the
analog ground plane should be allowed to run under the
AD7366-5/AD7367-5 to avoid noise coupling. The power
supply lines to the AD7366-5/AD7367-5 should use as large
a trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line.
To avoid radiating noise to other sections of the board, com-
ponents such as clocks with fast switching signals, should be
shielded with digital ground and should never be run near the
analog inputs. Avoid crossover of digital and analog signals. To
reduce the effects of feedthrough within the board, traces should
be run at right angles to each other. A microstrip technique is
the best method, but its use may not be possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes, and signals are placed on the
other side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to AGND. To achieve the best results from
these decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 µF capacitors should have a low effective series resistance
(ESR) and low effective series inductance (ESI), such as is typical
of common ceramic and surface mount types of capacitors. These
low ESR, low ESI capacitors provide a low impedance path to
ground at high frequencies to handle transient currents due to
internal logic switching.
EVALUATING THE AD7366-5/AD7367-5
Evaluation boards for the AD7366 and AD7367, the
EVAL-AD7366CBZ and EVAL-AD7367CBZ, can also be
used to evaluate the performance of the AD7366-5 and
AD7367-5, respectively. These evaluation boards can be
used in conjunction with EVAL-CONTROL BRD2 to
provide a full-featured evaluation platform.
