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SC16C850VIBS,128

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
SC16C850V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 19 January 2011 28 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.9 Extra Feature Control Register (EFCR)
This is a write-only register, and it allows the software access to these registers:
First Extra Register Set, Second Extra Register Set, Transmit FIFO Level Counter
(TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT).
Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can
only be accessed if EFCR[2:1] are zeroes.
7.10 Scratchpad Register (SPR)
The SC16C850V provides a temporary data register to store 8 bits of user information.
7.11 Division Latch (DLL and DLM)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
7.12 Transmit FIFO Level Count (TXLVLCNT)
This register is a read-only register. It reports the number of spaces available in the
transmit FIFO.
7.13 Receive FIFO Level Count (RXLVLCNT)
This register is a read-only register. It reports the fill level of the receive FIFO (the number
of characters in the RXFIFO).
Table 22. Extra Feature Control Register bits description
Bit Symbol Description
7:3 EFCR[7:3] reserved
2:1 EFCR[2:1] Enable Extra Feature Control bits
00 = General Register Set is accessible
01 = First Extra Register Set is accessible
10 = Second Extra Register Set is accessible
11 = reserved
0 EFCR[0] Enable TXLVLCNT and RXLVLCNT access
0 = TXLVLCNT and RXLVLCNT are disabled
1 = TXLVLCNT and RXLVLCNT are enabled and can be read
SC16C850V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 19 January 2011 29 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.14 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bit 0 through bit 4 provide single or dual character software flow control selection. When
the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential numbers.
[1] Enhanced function control bits: IER[7:4], ISR[5:4], FCR[5:4] and MCR[7:5].
Table 23. Enhanced Feature Register bits description
Bit Symbol Description
7 EFR[7] Automatic CTS flow control.
logic 0 = automatic CTS flow control is disabled (normal default condition)
logic 1 = enable automatic CTS flow control. Transmission will stop when
CTS goes to a logical 1. Transmission will resume when the CTS signal
returns to a logical 0.
6 EFR[6] Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be
generated when the receive FIFO is filled to the programmed trigger level and
RTS
will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when
data is unloaded below the next lower trigger level (programmed trigger level 1).
The state of this register bit changes with the status of the hardware flow
control. RTS
functions normally when hardware flow control is disabled.
logic 0 = automatic RTS flow control is disabled (normal default condition)
logic 1 = enable automatic RTS flow control
5 EFR[5] Special Character Detect.
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. The SC16C850V compares each
incoming receive character with Xoff2 data. If a match exists, the received
data will be transferred to FIFO and ISR[4] will be set to indicate detection of
special character. Bit-0 in the X-registers corresponds with the LSB bit for the
receive character. When this feature is enabled, the normal software flow
control must be disabled (EFR[3:0] must be set to a logic 0).
4 EFR[4] Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and
MCR[7:5] can be modified and latched. After modifying any bits in the enhanced
registers, EFR[4] can be set to a logic 0 to latch the new values. This feature
prevents existing software from altering or overwriting the SC16C850V
enhanced functions.
logic 0 = disable/latch enhanced features
[1]
logic 1 = enables the enhanced functions
[1]
. When this bit is set to a logic 1,
all enhanced features of the SC16C850V are enabled and user settings
stored during a reset will be restored.
3:0 EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming these
bits. See Table 24
.
SC16C850V All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 19 January 2011 30 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
[1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
7.15 Transmit Interrupt Level register (TXINTLVL)
This 8-bit register is used store the transmit FIFO trigger levels used for interrupt
generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.
Table 25
shows trigger level register bit settings.
[1] For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
7.16 Receive Interrupt Level register (RXINTLVL)
This 8-bit register is used store the receive FIFO trigger levels used for interrupt
generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.
Table 26
shows trigger level register bit settings.
Table 24. Software flow control functions
[1]
Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls
0 0 X X No transmit flow control
1 0 X X Transmit Xon1/Xoff1
0 1 X X Transmit Xon2/Xoff2
1 1 X X Transmit Xon1 and Xon2/Xoff1 and Xoff2
X X 0 0 No receive flow control
X X 1 0 Receiver compares Xon1/Xoff1
X X 0 1 Receiver compares Xon2/Xoff2
1 0 1 1 Transmit Xon1/Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0 1 1 1 Transmit Xon2/Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1 1 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Table 25. TXINTLVL register bits description
Bit Symbol Description
7:0 TXINTLVL[7:0] This register stores the programmable transmit interrupt trigger levels for
128-byte FIFO mode.
[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 26. RXINTLVL register bits description
Bit Symbol Description
7:0 RXINTLVL[7:0] This register stores the programmable receive interrupt trigger levels for
128-byte FIFO mode.
[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
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SC16C850VIBS,128

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Buy SC16C850VIBS,128
Manufacturer:
NXP Semiconductors
Description:
IC UART SINGLE W/FIFO 32-HVQFN
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