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SC16C850VIBS,128
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P45
P46-P48
SC16C850V
All informatio
n provided in thi
s document is su
bject to legal dis
claimers.
© NXP B.V
. 201
1. All rights reserved.
Product data sheet
Rev
. 5 — 19 Janua
ry 201
1
37 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, Ir
DA, and XScal
e VLIO bus in
terface
10.1
Timing diagrams
Fig 7.
General write timing
upper address
002aac35
4
AD7 to AD0
CS
LLA
IOW
lower address
data
t
w(LLA)
t
su(A-LLAH)
t
h(LLAH-A)
t
d(CS-LLAH)
t
w(IOW)
t
d(IOW)
t
su(D-IOWH)
t
h(IOWH-D)
t
d(LLAH-IOWL)
Fig 8.
General read timing
upper address
002aac35
5
AD7 to AD0
CS
LLA
IOR
lower address
data
t
w(LLA)
t
su(A-LLAH)
t
h(LLAH-A)
t
w(IOR)
t
d(IOR-D
V)
t
d(IOR)
t
dis(IOR-QZ)
t
d(LLAH-IORL)
t
d(CS-LLAH)
SC16C850V
All informatio
n provided in thi
s document is su
bject to legal dis
claimers.
© NXP B.V
. 201
1. All rights reserved.
Product data sheet
Rev
. 5 — 19 Janua
ry 201
1
38 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, Ir
DA, and XScal
e VLIO bus in
terface
Fig 9.
Modem input/output timing
t
d(IOW
-Q)
change of state
t
d(IOR-INTL)
002aac55
9
t
d(modem-INT)
change of state
change of state
change of state
active
active
active
activ
e
active
active
active
change of state
RTS
DTR
IOW
CD
CTS
DSR
INT
IOR
RI
t
d(modem-INT)
t
d(modem-INT)
Fig 10.
External clock timing
external clock
002aac35
7
t
w(clk)
t
WL
t
WH
f
XTAL1
1
t
wc
l
k
()
--------------
-
=
SC16C850V
All informatio
n provided in thi
s document is su
bject to legal dis
claimers.
© NXP B.V
. 201
1. All rights reserved.
Product data sheet
Rev
. 5 — 19 Janua
ry 201
1
39 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, Ir
DA, and XScal
e VLIO bus in
terface
Fig 1
1.
Receive timing
D0
D1
D2
D3
D4
D5
D6
D7
active
active
16 baud rate clock
002aac56
0
RX
INT
IOR
t
d(IOR-INTL)
t
d(stop-INT)
5 data bits
6 data bits
7 data bits
stop
bit
parity
bit
star
t
bit
data bits (0 to 7)
next
data
star
t
bit
Fig 12.
T
ransmit timing
active
transmitter ready
active
16 baud rate clock
002aac56
1
t
d(IOW
-INTL)
INT
IOW
active
D0
D1
D2
D3
D4
D5
D6
D7
TX
5 data bits
6 data bits
7 data bits
stop
bit
parity
bit
star
t
bit
data bits (0 to 7)
next
data
star
t
bit
t
d(start-INT)
t
d(IOW
-TX)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P45
P46-P48
SC16C850VIBS,128
Mfr. #:
Buy SC16C850VIBS,128
Manufacturer:
NXP Semiconductors
Description:
IC UART SINGLE W/FIFO 32-HVQFN
Lifecycle:
New from this manufacturer.
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