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IR1152 Pin Description
Pin COM: This is ground potential pin of the IC.
All internal devices are referenced to this point.
Pin COMP: External circuitry from this pin to
ground compensates the system voltage loop and
programs the soft start time. The COMP pin is
essentially the output of the voltage error amplifier.
The voltage loop error signal V
m
used in the control
algorithm is derived from V
COMP
(V
m
=V
COMP
V
COMP,START
). V
COMP
is actively discharged using an
internal resistance to below V
COMP,START
threshold
whenever the IC is pushed into Stand-by mode
(BOP or OLP condition) or UVLO/Sleep mode. The
gate drive output and logic functions of the IC are
inactive if VCOMP is less than V
COMP,START
. Also
during start-up, the VCOMP voltage has to be less
than V
COMP,START
in order to commence operation
(i.e. a pre-bias on VCOMP will not allow IC to
commence operation).
Pin ISNS: ISNS pin is tied to the input of the
current sense amplifier of the IC. The voltage at
this pin, which provides the current sense
information to the IC, has to be a negative voltage
wrt the COM pin. Also since the IC is based on
average current mode, the entire inductor current
information is necessary. A current sense resistor,
located below system ground along the return path
to the bridge rectifier, is the preferred current
sensing method. ISNS pin is also the inverting input
to the cycle-by-cycle peak current limit comparator.
Whenever V
ISNS
exceeds V
ISNS(PK)
threshold in
magnitude, the gate drive is instantaneously
disabled. Any external filtering of the ISNS pin must
be performed carefully in order to ensure that the
integrity of the current sense signal is maintained
for cycle-by-cycle peak current limit protection.
Pin BOP (Brown-out Protection): This pin is used
to sense the rectified AC input line voltage through
a resistor divider/capacitor network which is in
effect a voltage division and averaging network,
representing a scaled down signal of the average
rectified input voltage (average DC voltage + 2xf
AC
ripple). During start-up the BOP pin voltage has to
exceed V
BOP(EN)
in order to enable the IC to exit
Stand-by mode and enter normal operation. A
Brown-out situation is detected whenever the pin
voltage falls below V
BOP
and the IC is pushed into
Stand-by mode. Subsequently the pin has to
exceed V
BOP(EN)
for the IC to exit Stand-by and
resume normal operation.
Pin OVP/EN: The OVP/EN pin is connected to the
non-inverting input of the OVP(OVP) overvoltage
comparator shown in the block diagram and thus is
used to detect output overvoltage situations. The
output voltage information is communicated to the
OVP pin using a resistive divider. This pin also
serves the second purpose of an ENABLE pin. The
OVP/EN pin can be used to activate the IC into
“micropower sleep” mode by pulling the voltage on
this pin below the VSLEEP threshold. The OVP/EN
pin can be used to activate the IC into “micropower
sleep” mode by pulling the voltage on this pin below
the V
SLEEP
threshold.
Pin VFB: The converter output voltage is sensed
via a resistive divider and fed into this pin. VFB pin
is the inverting input of the output voltage error
amplifier. The non-inverting input of this amplifier is
connected to an internal 5V reference. The
impedance of the divider string must be low enough
that it does not introduce substantial error due to the
input bias currents of the amplifier, yet high enough
to minimize power dissipation. Typical value of
external divider impedance will be 2M. The VFB
pin is also connected to the non-inverting input of
the OVP(VFB) overvoltage comparator as shown in
the block diagram and is used to detect output
overvoltage situations. Finally, VFB pin is also the
inverting input to the Open Loop comparator. The IC
is held in Stand-by Mode whenever VFB pin voltage
is below VOLP threshold. IC current consumption is
a few mA in this mode.
Pin VCC: This is the supply voltage pin of the IC
and sense node for the undervoltage lock out circuit.
It is possible to turn off the IC by pulling this pin
below the minimum turn off threshold voltage,
VCC(UVLO) without damage to the IC. This pin is
not internally clamped.
Pin GATE: This is the gate drive output of the IC.
This drive voltage is internally clamped to 13V(Typ)
and provides a drive current of ±0.75A peak with
matched rise and fall times.
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IR1152 Modes of operation
Referenced to States & Transition Diagram
UVLO/Sleep Mode: The IC is in the UVLO/Sleep
mode when VCC pin voltage is below V
CC,ON
at
start-up or when VCC pin voltage drops below
V
CC,UVLO
during normal operation or when OVP/EN
pin voltage is below V
SLEEP
. The UVLO/Sleep
mode is accessible from any other state of
operation. This mode can be actively invoked by
pulling the OVP/EN pin below V
SLEEP
even if VCC
pin voltage is above V
CC,ON
. In the UVLO/Sleep
state, the gate drive circuit is inactive, most of the
internal circuitry is unbiased and the IC draws a
quiescent current of I
SLEEP
which is less than
75uA. Also, the internal logic of the IC ensures
that whenever the Sleep mode is actively invoked,
the COMP pin is actively discharged below
V
COMP,START
threshold prior to entering the sleep
mode, in order to facilitate soft-start upon
resumption of operation.
Stand-by Mode: The IC is placed in Stand-by
mode whenever an Open-loop and/or a Brown-out
situation is detected. A Brown-out situation is
sensed when BOP pin voltage is less than
V
BOP(EN)
prior to system start-up and when BOP
pin voltage drops below V
BOP
after start-up. An
Open-loop situation is sensed anytime VFB pin
voltage is less than V
OLP
. All internal circuitry is
biased in the Stand-by Mode, but the gate is
inactive and the IC draws a few mA of current.
This state is accessible from any other state of
operation of the IC. COMP pin is actively
discharged to below V
COMP,START
whenever this
state is entered from normal operation in order to
facilitate soft-start upon resumption of operation.
Soft Start Mode: During system start-up, the soft-
start mode is activated once the VCC voltage has
exceeded V
CC,ON
, the VFB pin voltage has
exceeded V
OLP
and BOP pin voltage has
exceeded V
BOP(EN)
and VCOMP voltage is less
than V
COMP,START
i.e. a pre-bias on COMP pin
greater than V
COMP,START
threshold will not allow IC
to commence operation. The soft start time is the
time required for the VCOMP voltage to charge
through its entire dynamic range i.e. through
V
COMP,EFF
. As a result, the soft-start time is
dependent upon the component values selected
for compensation of the voltage loop on the
COMP pin. To an extent, keeping in mind the
voltage feedback loop considerations, the soft-
system start time is programmable.
As VCOMP voltage rises gradually, the IC allows
a higher and higher RMS current into the PFC
converter. This controlled increase of the input
current amplitude contributes to reducing system
component stress during start-up.
Normal Mode: The IC enters the normal
operating mode once the soft start transition has
been completed (for all practical purposes there is
essentially no difference between the soft-start
and normal modes). At this point the gate drive is
switching and all protection functions of the IC are
active. If, from the normal mode, the IC is pushed
into either a Stand-by mode or UVLO/Sleep mode
then COMP pin is actively discharged below
V
COMP,START
and system will go through soft-start
upon resumption of operation.
OVP Mode: The IC enters OVP mode whenever
an overvoltage condition is detected. A system
overvoltage condition is recognized when VFB
and/or OVP/EN pin voltage exceeds V
OVP
threshold. When this happens the IC immediately
disables the gate drive and holds it in that state.
The gate drive is re-enabled only when both
OVP/EN and VFB pin voltages are less than
V
OVP(RST)
threshold. This state is accessible from
both the soft start and normal modes of operation.
IPK LIMIT Mode: The IC enters IPK LIMIT mode
whenever the magnitude of ISNS pin voltage
exceeds the V
ISNS(PK)
threshold triggering cycle-by-
cycle peak over-current protection. When this
happens, the IC immediately disables the gate
drive and holds it in that state. Gate drive is re-
enabled when magnitude of ISNS pin voltage
drops below V
ISNS(PK)
threshold. This state is
accessible from both the soft start and normal
modes of operation.
IR1152S
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State & Transitions Diagram
AC POWER ON
Gate Inactive
Internal Circuits
Unbiased
UVLO/SLEEP
MODE
Gate Inactive
Internal Circuits Biased
Vcomp Discharged
STAND – BY
MODE
Gate Inactive
Internal Circuits Biased
Vcomp Discharged
SOFT START
Gate Active
Oscillator Active
C
Z
Charging
V
COMP
Rising
V
FB
< V
OLP
OR
V
BOP
< V
BOP
(VTH)
NORMAL
Gate Active
Oscillator Active
V
FB
< V
OLP
OR
V
BOP
< V
BOP
(VTH)
OVP FAULT
Present PulseTerminated
Gate Inactive
Oscillator Active
IPK LIMIT
FAULT
Present PulseTerminated
Gate Inactive
Oscillator Active
V
CC
> V
CCON
AND
V
OVP
> V
SLEEP
V
FB
> V
OLP
AND
V
BOP
> V
BOP(EN)
AND
V
COMP
< V
COMP,START
Cz fully charged
V
OVP
> V
OVP
(VTH)
OR
V
FB
> V
OVP
(VTH)
V
OVP
< V
OVP(RST)
AND
V
FB
< V
OVP(RST)
V
CC
< V
CC UVLO
OR
V
OVP
< V
SLEEP
V
CC
< V
CC UVLO
OR
V
OVP
< V
SLEEP
|V
ISNS
| > |V
ISNS(PK)
|
|V
ISNS
| < |V
ISNS(PK)
|
V
BOP
< V
BOP
(VTH)
V
CC
< V
CC UVLO
OR
V
OVP
< V
SLEEP
V
CC
< V
CC UVLO
OR
V
OVP
<V
SLEEP
V
CC
< V
CC UVLO
OR
V
OVP
< V
SLEEP
V
FB
< V
OLP
OR
V
BOP
< V
BOP
(VTH)
|V
ISNS
| > |V
ISNS(PK)
|
|V
ISNS
| < |V
ISNS(PK)
|

IR1152STRPBF

Mfr. #:
Manufacturer:
Infineon / IR
Description:
Power Factor Correction - PFC OCC PFC Cntrl Fix Frequency
Lifecycle:
New from this manufacturer.
Delivery:
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