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ICS889831AKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
889831AK www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005
13
Integrated
Circuit
Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
3.3V
C5
R7
133
R9
133
3.3V
3.3V
+
-
R6
82.5
+
-
LVPECL
Zo = 50
Zo = 50
3.3V
R4
82.5
C6
R1
100
3.3V
C1
0.1u
Zo = 50
C2
0.1u
R10
82.5
R5
133
3.3V
Zo = 50
R3
133
R2
100
Zo = 50
U1
ICS889831
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Q1
nQ1
Q2
nQ2
Q3
nQ3
VCC
EN
nIN
VREF_AC
VT
IN
VEE
VCC
Q0
nQ0
2.5V
R8
82.5
Zo = 50
FIGURE 8. ICS889831 APPLICATION SCHEMATIC EXAMPLE
SCHEMATIC EXAMPLE
Figure 8
shows a schematic example of the ICS889831. This
schematic provides examples of input and output handling. The
ICS889831 input has built-in 50Ω termination resistors. The in-
put can directly accept various types of differential signal with-
out AC couple. For AC couple termination, the ICS889831 also
provides the VREF_AC pin for proper offset level after the AC
couple. This example shows the ICS889831 input driven by a
2.5V LVPECL driver with AC couple. The ICS889831 outputs
are LVPECL driver. In this example, we assume the traces are
long transmission line and the receiver is high input impedance
without built-in matched load. An example of 3.3V LVPECL ter-
mination is shown in this schematic. Additional termination ap-
proaches are shown in the LVPECL Termination Application Note.
889831AK www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005
14
Integrated
Circuit
Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
θθ
θθ
θ
JA
vs. 0 Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 51.5°C/W
TABLE 6. THERMAL RESISTANCE
θθ
θθ
θ
JA
FOR 16-PIN VFQFN, FORCED CONVECTION
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS839831.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS889831 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.63V * 60mA = 217.8mW
• Power (outputs)
MAX
= 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30.94mW = 123.8mW
• Power Dissipation at built-in terminations: Assume the input is driven by a 3.3V SSTL driver as shown in Figure 5E
and estimated approximately 1.75V drop across IN and nIN.
Total Power Dissipation for the two 50Ω built-in terminations is: (1.75V)
2
/ (50Ω + 50Ω) = 30.6mW
Total Power
_MAX
(3.63V, with all outputs switching) = 217.8mW + 123.8mW + 30.6mW = 372.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming a
moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.372W * 51.5°C/W = 104°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
889831AK www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005
15
Integrated
Circuit
Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 9.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CC
- 2V.
• For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.935V
(V
CC_MAX
- V
OH_MAX
)
= 0.935V
• For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.67V
(V
CC_MAX
- V
OL_MAX
)
= 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))
/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))
/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
FIGURE 9. LVPECL DRIVER CIRCUIT AND TERMINATION
VOUT
Q1
VCC - 2V
RL
50
VCC
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

ICS889831AKLF

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IC CLK BUFFER 1:4 2.1GHZ 16VFQFN
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