LTC1040CSW#PBF

7
LTC1040
1040fa
1A
100mV
APPLICATIO S I FOR ATIO
WUUU
Offset Voltage Error
The errors due to offset, common mode, power supply
variation, gain and temperature are all included in the
offset voltage specification. This makes it easy to compute
the error when using the LTC1040.
Example: error computation for Figure 4.
Assume: 2.8V V
S
6V.
Then total worst-case error is:
Note: If source resistance exceeds 10k, bypass
capacitors should be used and the associated errors must
be included.
Pulsed Power (V
P-P
) Output
It is often desirable to use comparators with resistive
networks such as bridges. Because of the extremely low
power consumption of the LTC1040, the power consumed
by these resistive networks can far exceed that of the
device itself.
At low sample rates the LTC1040 spends most of its time
off. To take advantage of this, a pulsed power (V
P-P
) output
is provided. V
P-P
is switched to V
+
when the comparator
is on and to a high impedance (open circuit) when the
comparator is off. The ON time is nominally 80µs.
Figure 5 shows the V
P-P
output circuit.
The V
P-P
output voltage is not precise (see V
P-P
Output
Voltage versus Load Current curve). There are two ways
V
P-P
can be used to power external networks without
excessive errors: (1) ratiometric networks and (2) fast
settling references.
In a ratiometric network, the inputs are all proportional to
V
P-P
(see Figure 6). Consequently, for small changes, the
absolute value of V
P-P
does not affect accuracy.
It is critical that the inputs to the LTC1040 completely
settle within 4µs of the start of the comparison cycle and
that they do not change during the 80µs ON time. When
driving resistive networks with V
P-P
, capacitive loading on
the network should be minimized to meet the 4µs settling
time requirement. It is not recommended that V
P-P
be used
to drive networks with source impedances, as seen by the
inputs, of greater than 10k.
In applications where an absolute reference is required,
the V
P-P
output can be used to drive a fast settling
reference. The LT1009 2.5V reference, ideal in this
application, settles in approximately 2µs (see Figure 7).
The current through R1 must be large enough to supply
the LT1009 minimum bias current (1mA) and the load
current, I
L
.
LTC1040 • AI05
80µs
COMPARATOR ON TIME
18
V
+
917
GND
Q1 P1
V
P-P
Figure 7. Driving Reference with V
P-P
Output
Figure 6. Ratiometric Network Driven by
V
P-P
Figure 5. V
P-P
Output Switch
= ±6mA
I
L (ERROR)
= ± (100mV • 0.001 + 0.5mV) •
↑↑
Tracking Error V
OS
I
L (ERROR)
% = • 100 = ± 0.6%.
6mA
1A
V
IN
V
TRIP
OUTPUT
V
P-P
OUTPUT
LTC1040 • AI06
–+
+
+
1/2
LTC1040
V
IN
I
L
V
P-P
OUTPUT
LTC1040 • AI07
+
+
1/2
LTC1040
R2
R3
LT1009
R1
8
LTC1040
1040fa
Output Logic
In addition to the normal outputs (A
OUT
and B
OUT
), two
additional outputs, A + B and ON/0FF, are provided (see
Figure 8 and Table 1). All logic is powered from V
+
and
ground, thus input and output logic levels are independent
of the V
supply. The LTC1040 is directly compatible with
CMOS logic and is TTL compatible for 4.75V V
+
5.25V.
No external pull-up resistors are required.
ΣA INPUTS ΣB INPUTS A
OUT
B
OUT
A + B ON/OFF
++HHLL
+–HLLL
–+LHLH
––LLHI*
*I = indeterminate. When both A and B outputs are low, the ON/OFF output
remains in the state it was in prior to entering A
OUT
= B
OUT
= L.
Using External Strobe
A positive pulse on the strobe input, with the 0SC input tied
to ground, will initiate a comparison cycle. The STROBE
input is edge-sensitive and pulse widths of 50ns will
typically trigger the device.
APPLICATIO S I FOR ATIO
WUUU
Because of the sampling nature of the LTC1040, some
sensitivity exists between the offset voltage and the falling
edge of the input strobe. When the falling edge of the
strobe signal falls within the comparator’s active time
(80µs after rising edge), offset changes of as much as 2mV
can occur. To eliminate this problem, make sure the strobe
pulse width is greater than the response time, t
D
.
Using Internal Strobe
An internal oscillator allows the LTC1040 to strobe itself.
The frequency of oscillation, and hence sampling rate, is
set by an external RC network (see typical curve of
Sampling Rate vs R
EXT
, C
EXT
).
For self-oscillation, the STROBE pin must be tied to
ground. The external RC network is connected as shown
in Figure 9.
To assure oscillation, R
EXT
must be between 100k and
10M. There is no limit to the size of C
EXT
.
R
EXT
is very important in determining the power
consumption. The average voltage at the oscillator pin is
approximately V
+
/2. The power consumed by R
EXT
is then:
P
REXT
= (V
+
/2)
2
/R
EXT
.
LTC1040 • AI08
B
OUT
A
OUT
A + B
ON/OFF
80µs
COMPARATOR A
OUTPUT
COMPARATOR B
OUTPUT
STROBE
D
D
C
CQ
Q
2
4
3
15
R
EXT
C
EXT
LTC1040 • AI09
1
9
18
17
16
10
LTC1040
V
+
Figure 9. External RC Connection
Figure 8. LTC1040 Logic Diagram
Table 1. Output Logic Truth Table
Example: R
EXT
= 1M, V
+
5V, P
REXT
= (2.5)
2
/10
6
=
6.25 • 10
–6
W.
This is about four times the power consumed by the
LTC1040 at V
+
= 5V and f
S
= 1 sample/second. Where
power is a premium R
EXT
should be made as large as
possible. Note that the power consumed by R
EXT
is
not
a
function of f
S
or C
EXT
.
9
LTC1040
1040fa
TYPICAL APPLICATIO S
U
Complete Heating/Cooling Automatic Thermostat
5k
TEMP
ADJUST
6.81k
4.32k 4.99k
82k*
20M
82k*
SEPARATION
(20mV)
LTC1040 • TA03
+
+
COMP B
LTC1040
+
+
COMP A
5
17 18
4
3
15
16
10
0.1µF
10M
COOL
HEAT
9
6
7
8
14
13
12
11
20M
THERMISTOR # 44007
YELLOW SPRINGS INSTRUMENT CO., INC.
HYSTERESIS = 5V • = 20mV
5V AT 0.85µA
*
82k
20M
28°C
27°C
HEAT
COOL
TIME
LTC1040 • TA04
HEATER ON
TEMPERATURE
HEATER OFF
AIRCONDITIONING OFF
AIRCONDITIONING ON
HYSTERESIS
HYSTERESIS
SEPARATION
Window Comparator with Independent Window Limits and
Fully Floating Differential Input
Hysteresis Comparator with Fully Floating Differential Input
A
OUT
= “1” WHEN
V
IN
> V
U
B
OUT
= “1” WHEN
V
IN
< V
L
A+B = “1” WHEN
V
U
V
IN
V
L
LTC1040 • TA05
+
+
+
+
COMP A
COMP B
LTC1040
V
L
V
IN
V
U
V
IN
OUT = “0” WHEN V
IN
> V
U
= = 0.996 V
TRIP
+ 20mV
V
TRIP
LTC1040 • TA06
V
+
R2
2.49M
R1
10k
OUT
+
+
1/2 LTC1040
*
*
V
TRIP
R2 + (5V) R1
R1 + R2
OUT = “1” WHEN V
IN
< V1
=
TO CENTER HYSTERESIS ABOUT V
TRIP
,
FORCE THIS INPUT TO
HYSTERESIS/2 (10mV)
= 0.996V
TRIP
V
TRIP
R2
R1 + R2

LTC1040CSW#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Comparators Dual uP COMPARATOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet