MK2049-45ASILFTR

DATASHEET
3.3 VOLT COMMUNICATIONS CLOCK PLL MK2049-45A
IDT™
3.3 VOLT COMMUNICATIONS CLOCK PLL 1
MK2049-45A REV C 051310
Description
The MK2049-45A is a dual Phase-Locked Loop (PLL)
device which can provide frequency synthesis and jitter
attenuation. The first PLL is VCXO based and uses a
pullable crystal to track signal wander and attenuate input
jitter. The second PLL is a translator for frequency
multiplication. Basic configuration is determined by a
Mode/Frequency Selection Table. Loop bandwidth and
damping factor are programmable via external loop filter
component selection.
Buffer Mode accepts a 10 to 50 MHz input and will provide
a jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x
ICLK. In this mode the MK2049-45A is ideal for filtering jitter
from high frequency clocks.
In External Mode, ICLK accepts an 8 kHz clock and will
produce output frequencies from a table of common
communciations clock rates, CLK and CLK/2. This allows
for the generation of clocks frequency-locked to an 8 kHz
backplane clock, simplifying clock synchronization in
communications systems.
The MK2049-45A can be dynamically switched between T1,
E1, T3, E3 outputs with the same 24.576 MHz crystal.
IDT can customize these devices for many other different
frequencies. Contact your IDT representative for more
details.
Features
Packaged in 20-pin SOIC
3.3 V + 5% operation
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
Accepts multiple inputs: 8 kHz backplane clock, or 10 to
50 MHz
Locks to 8 kHz + 100 ppm (External mode)
Buffer Mode allows jitter attenuation of 10 - 50 MHz input
and x1 / x0.5 or x1 / x2 outputs
Exact internal ratios enable zero ppm error
Output rates include T1, E1, T3, E3, and OC3
submultiples
Pb (lead) free package
See also the MK2049-34 and MK2049-36
Block Diagram
Charge
Pump
VCXO
X2X1ISET CAP2
Feedback
Divider (N)
Reference
Divider
(used in buffer
mode only)
ICLK
Reference
Divider
Phase
Detector
VCXO
PLL
Feedback
Divider
VCO
Translator
PLL
CLK
CAP1
Output
Divider
Divide
by 2
CLK/2
8k
R
S
R
SET
C
P
C
S
Optional Crystal Load Caps
Divider Value
Look-up Table
FS3:0
4
C
L
C
L
External Pullable Crystal
MK2049-45A
3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER
IDT™
3.3 VOLT COMMUNICATIONS CLOCK PLL 2
MK2049-45A REV C 051310
Pin Assignment
Pin Descriptions
16
1
15
2
14
FS1 FS0
3
13
X2
4
12
X1
RES
5
11
VDD
6
CAP2
7
FCAP
8
VDD
GND
CAP1
VDD
GND
GND
CLK
ICLK
9
10
CLK/2
FS3
8k
FS2
20
19
18
17
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 FS1 Input Frequency select 1. Determines CLK input/outputs per table on page 2.
Internal pull-up resistor.
2 X2 Input Crystal connection. Connect to a MHz crystal as shown in table on page 2.
3 X1 Input Crystal connection. Connect to a MHz crystal as shown in table on page 2.
4 VDD Power Power supply. Connect to +3.3 V.
5 FCAP - Filter capacitor. Connect a 1000 pF ceramic capacitor to ground.
6 VDD Power Power supply. Connect to +3.3 V.
7 GND Power Connect to ground
8 CLK Output Clock output determined by status of FS3:0 per tables on page 2.
9 CLK/2 Output Clock output determined by status of FS3:0 per tables page 2. Always 1/2 of
CLK.
10 8k Output Recovered 8 kHz clock output.
11 FS2 Input Frequency select 2. Determines CLK input/outputs per table on page 2.
Internal pull-up resistor.
12 FS3 Input Frequency select 3. Determines CLK input/outputs per table on page 2.
Internal pull-up resistor.
13 ICLK Input Input clock connection. Connect to 8 kHz backplane or MHz clock.
14 GND Power Connect to ground.
15 VDD Power Power Supply. Connect to +3.3 V.
16 CAP1 Loop
Filter
Connect the loop filter capacitors and resistor between this pin and CAP2.
17 GND Power Connect to ground.
MK2049-45A
3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER
IDT™
3.3 VOLT COMMUNICATIONS CLOCK PLL 3
MK2049-45A REV C 051310
Output Decoding Table - External Mode (MHz)
Output Decoding Table - Buffer Mode (MHz)
0 = connect directly to ground, 1 = connect directly to VDD
Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
Functional Description
The MK2049-45A is a clock generator IC that generates an
output clock directly from an internal VCXO circuit which
works in conjunction with an external quartz crystal. The
VCXO is controlled by an internal PLL (Phase Locked Loop)
circuit, enabling the device to perform clock regeneration
from an input reference clock. The MK2049-45A is
configured to provide a high frequency communications
reference clock output from an 8 kHz input clock or to jitter
attenuate and buffer a high frequency input clock. There are
14 selectable output frequencies and two buffer mode
selections. Please refer to the Output Clock Selection Table
on Page 2.
Most typical PLL clock devices use an internal VCO (Voltage
Controlled Oscillator) for output clock generation. By using
a VCXO with an external crystal, the MK2049-45A is able to
18 CAP2 Loop
Filter
Connect the loop filter capacitors and resistor between this pin and CAP1.
19 RES - Connect a resistor to ground. See table.
20 FS0 Input Frequency select 0. Determines CLK input/outputs per table on page 2.
Internal pull-up resistor.
ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8k
Crystal
Used (MHz) N
8 kHz00001.5443.0888 kHz24.576 3072
8 kHz00012.0484.0968 kHz24.576 3072
8 kHz001022.36844.7368 kHz24.576 3072
8 kHz001117.18434.3688 kHz24.576 3072
8 kHz010019.4438.888 kHz 19.44 2430
8 kHz0101 12.8 25.6 8 kHz 25.6 3200
8 kHz011025.9251.848 kHz 17.28 2160
8 kHz01114.0968.1928 kHz16.384 2048
8 kHz100018.52837.0568 kHz24.704 3088
8 kHz100112.35224.7048 kHz24.704 3088
8 kHz101024.57649.1528 kHz16.384 2048
8 kHz101116.38432.7688 kHz16.384 2048
8 kHz110017.2834.568 kHz 17.28 2160
8 kHz1101 62.5 125 8 kHz 25 3125
Pin
Number
Pin
Name
Pin
Type
Pin Description
ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8k Crystal N
20 - 501110ICLK2*ICLKN/AICLK/23
10 - 251111ICLK/2ICLKN/AICLK 3

MK2049-45ASILFTR

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 3.3 VOLT COMMUNICA. CLOCK VCXO PLL
Lifecycle:
New from this manufacturer.
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