MK2049-45A
3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER
IDT™
3.3 VOLT COMMUNICATIONS CLOCK PLL 8
MK2049-45A REV C 051310
Note 1: Minimum high or low time of input clock.
Note 2: For the 1.544 MHz and 2.048 MHz output selections, the input to output clock skew is not controlled nor
predictable and will change between power up cycles. Because it is dependent on the phase relationship between
the output and feedback divider states following power up, the input to output clock skew will remain stable during a
given power up cycle. If controlled input to output skew is desired for this output clock frequency please refer to the
MK2049 or MK2069 products.
Note 3: Input reference is the 8 kHz output from a Mitel/Zarlink MT9045 device in freerun mode
(SEL2:0 = 100, 19.44 MHz external crystal).
Marking Diagram (Pb free)
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and the week that the part was assembled.
3. “LF” designates Pb (lead) free package.
4. Bottom marking: country of origin.
Timing Jitter,
Filtered 65 kHz-1.3 MHz (OC-3)
t
jf
Referenced to
Mitel/Zarlink MT9045,
Note 3
230 ps
Frequency Error Relative to ICLK 0 ppm
Nominal Output Impedance Z
OUT
20
Parameter Symbol Conditions Min. Typ. Max. Units
1
10
11
20
2049-45ASILF
######
YYWW